2 * (C) Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
6 * Configuration settings for the Freescale S32V234 EVB board.
12 #include <asm/arch/imx-regs.h>
14 #define CONFIG_S32V234
18 #define GICD_BASE 0x7D001000
19 #define GICC_BASE 0x7D002000
21 #define CONFIG_REMAKE_ELF
22 #undef CONFIG_RUN_FROM_IRAM_ONLY
24 #define CONFIG_RUN_FROM_DDR1
25 #undef CONFIG_RUN_FROM_DDR0
27 /* Run by default from DDR1 */
28 #ifdef CONFIG_RUN_FROM_DDR0
29 #define DDR_BASE_ADDR 0x80000000
31 #define DDR_BASE_ADDR 0xC0000000
34 #define CONFIG_MACH_TYPE 4146
36 #define CONFIG_SKIP_LOWLEVEL_INIT
39 #define CONFIG_CMD_CACHE
41 #define CONFIG_SYS_FULL_VA
43 /* Enable passing of ATAGs */
44 #define CONFIG_CMDLINE_TAG
46 /* SMP Spin Table Definitions */
47 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
49 /* Generic Timer Definitions */
50 #define COUNTER_FREQUENCY (1000000000) /* 1000MHz */
51 #define CONFIG_SYS_FSL_ERRATUM_A008585
53 /* Size of malloc() pool */
54 #ifdef CONFIG_RUN_FROM_IRAM_ONLY
55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1 * 1024 * 1024)
57 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
60 #define CONFIG_FSL_LINFLEXUART
61 #define LINFLEXUART_BASE LINFLEXD0_BASE_ADDR
63 #define CONFIG_DEBUG_UART_LINFLEXUART
64 #define CONFIG_DEBUG_UART_BASE LINFLEXUART_BASE
66 /* Allow to overwrite serial and ethaddr */
67 #define CONFIG_ENV_OVERWRITE
68 #define CONFIG_SYS_UART_PORT (1)
70 #define CONFIG_FSL_USDHC
71 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR
72 #define CONFIG_SYS_FSL_ESDHC_NUM 1
74 #define CONFIG_CMD_MMC
75 /* #define CONFIG_CMD_EXT2 EXT2 Support */
80 #define CONFIG_CMD_MII
81 #define CONFIG_FEC_MXC
83 #define IMX_FEC_BASE ENET_BASE_ADDR
84 #define CONFIG_FEC_XCV_TYPE RMII
85 #define CONFIG_FEC_MXC_PHYADDR 0
88 #if 0 /* Disable until the FLASH will be implemented */
89 #define CONFIG_SYS_USE_NAND
92 #ifdef CONFIG_SYS_USE_NAND
93 /* Nand Flash Configs */
94 #define CONFIG_JFFS2_NAND
95 #define MTD_NAND_FSL_NFC_SWECC 1
96 #define CONFIG_NAND_FSL_NFC
97 #define CONFIG_SYS_NAND_BASE 0x400E0000
98 #define CONFIG_SYS_MAX_NAND_DEVICE 1
99 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
100 #define CONFIG_SYS_NAND_SELECT_DEVICE
101 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
104 #define CONFIG_LOADADDR 0xC307FFC0
106 #define CONFIG_EXTRA_ENV_SETTINGS \
107 "boot_scripts=boot.scr.uimg boot.scr\0" \
108 "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
109 "console=ttyLF0,115200\0" \
110 "fdt_file=s32v234-evb.dtb\0" \
111 "fdt_high=0xffffffff\0" \
112 "initrd_high=0xffffffff\0" \
113 "fdt_addr_r=0xC2000000\0" \
114 "kernel_addr_r=0xC307FFC0\0" \
115 "ramdisk_addr_r=0xC4000000\0" \
116 "ramdisk=rootfs.uimg\0"\
118 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
119 "update_sd_firmware_filename=u-boot.imx\0" \
120 "update_sd_firmware=" \
121 "if test ${ip_dyn} = yes; then " \
122 "setenv get_cmd dhcp; " \
124 "setenv get_cmd tftp; " \
126 "if mmc dev ${mmcdev}; then " \
127 "if ${get_cmd} ${update_sd_firmware_filename}; then " \
128 "setexpr fw_sz ${filesize} / 0x200; " \
129 "setexpr fw_sz ${fw_sz} + 1; " \
130 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
133 "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\0" \
134 "jtagboot=echo Booting using jtag...; " \
135 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
136 "jtagsdboot=echo Booting loading Linux with ramdisk from SD...; " \
137 "run loaduimage; run loadramdisk; run loadfdt;"\
138 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
139 "boot_net_usb_start=true\0" \
142 #define BOOT_TARGET_DEVICES(func) \
147 #define CONFIG_BOOTCOMMAND \
150 #include <config_distro_bootcmd.h>
152 /* Miscellaneous configurable options */
153 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
154 #define CONFIG_SYS_PROMPT "=> "
156 #define CONFIG_SYS_MEMTEST_START (DDR_BASE_ADDR)
157 #define CONFIG_SYS_MEMTEST_END (DDR_BASE_ADDR + 0x7C00000)
159 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
160 #define CONFIG_SYS_HZ 1000
162 #ifdef CONFIG_RUN_FROM_IRAM_ONLY
163 #define CONFIG_SYS_MALLOC_BASE (DDR_BASE_ADDR)
168 #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
171 /* Physical memory map */
172 /* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */
173 #define CONFIG_NR_DRAM_BANKS 1
174 #define PHYS_SDRAM (DDR_BASE_ADDR)
175 #define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
177 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
178 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
179 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
181 #define CONFIG_SYS_INIT_SP_OFFSET \
182 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
183 #define CONFIG_SYS_INIT_SP_ADDR \
184 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
186 /* environment organization */
187 #define CONFIG_ENV_SIZE (8 * 1024)
189 #define CONFIG_ENV_OFFSET (12 * 64 * 1024)
190 #define CONFIG_SYS_MMC_ENV_DEV 0
193 #define CONFIG_BOOTP_BOOTFILESIZE