2 * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
4 * Configuration settings for the Dave/DENX QongEVB-LITE board.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
14 /* High Level Configuration Options */
15 #define CONFIG_MX31 /* This is a mx31 */
18 #define CONFIG_DISPLAY_CPUINFO
19 #define CONFIG_DISPLAY_BOARDINFO
21 #define CONFIG_SYS_TEXT_BASE 0xa0000000
23 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
24 #define CONFIG_SETUP_MEMORY_TAGS
25 #define CONFIG_INITRD_TAG
28 * Size of malloc() pool
30 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024)
36 #define CONFIG_MXC_UART
37 #define CONFIG_MXC_UART_BASE UART1_BASE
39 #define CONFIG_MXC_GPIO
40 #define CONFIG_HW_WATCHDOG
41 #define CONFIG_IMX_WATCHDOG
43 #define CONFIG_MXC_SPI
44 #define CONFIG_DEFAULT_SPI_BUS 1
45 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
46 #define CONFIG_RTC_MC13XXX
49 #define CONFIG_POWER_SPI
50 #define CONFIG_POWER_FSL
51 #define CONFIG_FSL_PMIC_BUS 1
52 #define CONFIG_FSL_PMIC_CS 0
53 #define CONFIG_FSL_PMIC_CLK 100000
54 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
55 #define CONFIG_FSL_PMIC_BITLEN 32
59 #define CONFIG_QONG_FPGA
60 #define CONFIG_FPGA_BASE (CS1_BASE)
61 #define CONFIG_FPGA_LATTICE
62 #define CONFIG_FPGA_COUNT 1
64 #ifdef CONFIG_QONG_FPGA
67 #define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
69 /* Framebuffer and LCD */
71 #define CONFIG_CFB_CONSOLE
72 #define CONFIG_VIDEO_MX3
73 #define CONFIG_VIDEO_LOGO
74 #define CONFIG_VIDEO_SW_CURSOR
75 #define CONFIG_VGA_AS_SINGLE_DEVICE
76 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
77 #define CONFIG_SPLASH_SCREEN
78 #define CONFIG_CMD_BMP
79 #define CONFIG_BMP_16BPP
80 #define CONFIG_VIDEO_BMP_GZIP
81 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
84 #define CONFIG_CMD_USB
86 #define CONFIG_USB_EHCI /* Enable EHCI USB support */
87 #define CONFIG_USB_EHCI_MXC
88 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
89 #define CONFIG_MXC_USB_PORT 2
90 #define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
91 #define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
92 #define CONFIG_EHCI_IS_TDI
93 #define CONFIG_USB_STORAGE
94 #define CONFIG_DOS_PARTITION
95 #define CONFIG_SUPPORT_VFAT
96 #define CONFIG_CMD_EXT2
97 #define CONFIG_CMD_FAT
98 #endif /* CONFIG_CMD_USB */
101 * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
102 * initial TFTP transfer, should the user wish one, significantly.
104 #define CONFIG_ARP_TIMEOUT 200UL
106 #endif /* CONFIG_QONG_FPGA */
108 #define CONFIG_CONS_INDEX 1
109 #define CONFIG_BAUDRATE 115200
111 /***********************************************************
113 ***********************************************************/
114 #define CONFIG_CMD_CACHE
115 #define CONFIG_CMD_DATE
116 #define CONFIG_CMD_DHCP
117 #define CONFIG_CMD_MII
118 #define CONFIG_CMD_NAND
119 #define CONFIG_CMD_PING
120 #define CONFIG_CMD_SPI
121 #define CONFIG_CMD_UNZIP
123 #define CONFIG_BOARD_LATE_INIT
125 #define CONFIG_BOOTDELAY 5
127 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
129 #define CONFIG_EXTRA_ENV_SETTINGS \
131 "nfsargs=setenv bootargs root=/dev/nfs rw " \
132 "nfsroot=${serverip}:${rootpath}\0" \
133 "ramargs=setenv bootargs root=/dev/ram rw\0" \
134 "addip=setenv bootargs ${bootargs} " \
135 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
136 ":${hostname}:${netdev}:off panic=1\0" \
137 "addtty=setenv bootargs ${bootargs}" \
138 " console=ttymxc0,${baudrate}\0" \
139 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
140 "addmisc=setenv bootargs ${bootargs}\0" \
141 "uboot_addr=A0000000\0" \
142 "kernel_addr=A00C0000\0" \
143 "ramdisk_addr=A0300000\0" \
144 "u-boot=qong/u-boot.bin\0" \
145 "kernel_addr_r=80800000\0" \
147 "bootfile=qong/uImage\0" \
148 "rootpath=/opt/eldk-4.2-arm/armVFP\0" \
149 "flash_self=run ramargs addip addtty addmtd addmisc;" \
150 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
151 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
152 "bootm ${kernel_addr}\0" \
153 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
154 "run nfsargs addip addtty addmtd addmisc;" \
156 "bootcmd=run flash_self\0" \
157 "load=tftp ${loadaddr} ${u-boot}\0" \
158 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
159 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
160 " +${filesize};cp.b ${fileaddr} " \
161 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
162 "upd=run load update\0" \
163 "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \
164 "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \
168 * Miscellaneous configurable options
170 #define CONFIG_SYS_LONGHELP /* undef to save memory */
171 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
172 /* Print Buffer Size */
173 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
174 sizeof(CONFIG_SYS_PROMPT) + 16)
175 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
176 /* Boot Argument Buffer Size */
177 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
179 /* memtest works on first 255MB of RAM */
180 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
181 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000)
183 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
185 #define CONFIG_CMDLINE_EDITING
186 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
188 #define CONFIG_MISC_INIT_R
190 /*-----------------------------------------------------------------------
191 * Physical Memory Map
193 #define CONFIG_NR_DRAM_BANKS 1
194 #define PHYS_SDRAM_1 CSD0_BASE
195 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
202 extern void qong_nand_plat_init(void *chip);
203 extern int qong_nand_rdy(void *chip);
205 #define CONFIG_NAND_PLAT
206 #define CONFIG_SYS_MAX_NAND_DEVICE 1
207 #define CONFIG_SYS_NAND_BASE CS3_BASE
208 #define NAND_PLAT_INIT() qong_nand_plat_init(nand)
210 #define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
211 #define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
212 #define QONG_NAND_WRITE(addr, cmd) \
214 __REG8(addr) = cmd; \
217 #define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
218 #define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
219 #define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip))
221 /*-----------------------------------------------------------------------
222 * FLASH and environment organization
224 #define CONFIG_SYS_FLASH_BASE CS0_BASE
225 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
226 /* max number of sectors on one chip */
227 #define CONFIG_SYS_MAX_FLASH_SECT 1024
228 /* Monitor at beginning of flash */
229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
230 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
232 #define CONFIG_ENV_IS_IN_FLASH
233 #define CONFIG_ENV_SECT_SIZE 0x20000
234 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
235 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
237 /* Address and size of Redundant Environment Sector */
238 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
239 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
241 /*-----------------------------------------------------------------------
242 * CFI FLASH driver setup
244 /* Flash memory is CFI compliant */
245 #define CONFIG_SYS_FLASH_CFI
246 /* Use drivers/cfi_flash.c */
247 #define CONFIG_FLASH_CFI_DRIVER
248 /* Use buffered writes (~10x faster) */
249 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
250 /* Use hardware sector protection */
251 #define CONFIG_SYS_FLASH_PROTECTION
256 #define CONFIG_CMD_JFFS2
257 #define CONFIG_CMD_UBI
258 #define CONFIG_CMD_UBIFS
259 #define CONFIG_RBTREE
260 #define CONFIG_MTD_PARTITIONS
261 #define CONFIG_CMD_MTDPARTS
263 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
264 #define CONFIG_FLASH_CFI_MTD
265 #define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
267 #define MTDPARTS_DEFAULT \
268 "mtdparts=physmap-flash.0:" \
269 "512k(U-Boot),128k(env1),128k(env2)," \
270 "2304k(kernel),13m(ramdisk),-(user);" \
274 /* additions for new relocation code, must be added to all boards */
275 #define CONFIG_SYS_SDRAM_BASE 0x80000000
276 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
277 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
278 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
279 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
281 #define CONFIG_BOARD_EARLY_INIT_F
283 #endif /* __CONFIG_H */