Merge branch 'master' of git://www.denx.de/git/u-boot-imx
[oweals/u-boot.git] / include / configs / pr1.h
1 /*
2  * U-boot - Configuration file for PR1 Appliance
3  *
4  * based on bf537-stamp.h
5  * Copyright (c) Switchfin Org. <dpn@switchfin.org>
6  */
7
8 #ifndef __CONFIG_PR1_H__
9 #define __CONFIG_PR1_H__
10
11 #include <asm/config-pre.h>
12
13
14 /*
15  * Processor Settings
16  */
17 #define CONFIG_BFIN_CPU             bf537-0.3
18 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
19
20
21 /*
22  * Clock Settings
23  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
24  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
25  */
26 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
27 #define CONFIG_CLKIN_HZ                 25000000
28 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
29 /*                                                1 = CLKIN / 2         */
30 #define CONFIG_CLKIN_HALF               0
31 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
32 /*                                                1 = bypass PLL        */
33 #define CONFIG_PLL_BYPASS               0
34 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
35 /* Values can range from 0-63 (where 0 means 64)                        */
36 #define CONFIG_VCO_MULT                 24
37 /* CCLK_DIV controls the core clock divider                             */
38 /* Values can be 1, 2, 4, or 8 ONLY                                     */
39 #define CONFIG_CCLK_DIV                 1
40 /* SCLK_DIV controls the system clock divider                           */
41 /* Values can range from 1-15                                           */
42 #define CONFIG_SCLK_DIV                 5
43
44
45 /*
46  * Memory Settings
47  */
48 #define CONFIG_MEM_ADD_WDTH     11
49 #define CONFIG_MEM_SIZE         128
50
51 #define CONFIG_EBIU_SDRRC_VAL   0x306
52 #define CONFIG_EBIU_SDGCTL_VAL  0x8091998d
53
54 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
55 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
56 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
57
58 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
59 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)
60
61
62 /*
63  * Network Settings
64  */
65 #ifndef __ADSPBF534__
66 #define ADI_CMDS_NETWORK        1
67 #define CONFIG_BFIN_MAC
68 #define CONFIG_NETCONSOLE
69 #endif
70 #define CONFIG_HOSTNAME         pr1
71 #define CONFIG_TFTP_BLOCKSIZE   4404
72
73
74 /*
75  * Flash Settings
76  */
77 #define CONFIG_SYS_NO_FLASH     /* We have no parallel FLASH */
78
79
80 /*
81  * SPI Settings
82  */
83 #define CONFIG_BFIN_SPI
84 #define CONFIG_ENV_SPI_MAX_HZ   30000000
85 #define CONFIG_SF_DEFAULT_SPEED 30000000
86
87
88 /*
89  * Env Storage Settings
90  */
91 #define CONFIG_ENV_IS_IN_SPI_FLASH
92 #define CONFIG_ENV_OFFSET       0x10000
93 #define CONFIG_ENV_SIZE         0x2000
94 #define CONFIG_ENV_SECT_SIZE    0x10000
95 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
96
97
98 /*
99  * I2C Settings
100  */
101 #define CONFIG_SYS_I2C
102 #define CONFIG_SYS_I2C_ADI
103
104
105 /*
106  * NAND Settings
107  */
108 #define CONFIG_NAND_PLAT
109 #define CONFIG_SYS_NAND_BASE            0x20000000
110 #define CONFIG_SYS_MAX_NAND_DEVICE      1
111
112 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
113 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
114 #define BFIN_NAND_WRITE(addr, cmd) \
115         do { \
116                 bfin_write8(addr, cmd); \
117                 SSYNC(); \
118         } while (0)
119
120 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
121 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
122 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF9
123
124 /*
125  * Misc Settings
126  */
127 #define CONFIG_BAUDRATE         115200
128 #define CONFIG_RTC_BFIN
129 #define CONFIG_UART_CONSOLE     0
130 #define CONFIG_BOOTCOMMAND      "run nandboot"
131 #define CONFIG_BOOTDELAY        2
132 #define CONFIG_LOADADDR         0x2000000
133
134 /*
135  * Pull in common ADI header for remaining command/environment setup
136  */
137 #include <configs/bfin_adi_common.h>
138
139 /*
140  * Overwrite some settings defined in bfin_adi_common.h
141  */
142 #undef NAND_ENV_SETTINGS
143 #define NAND_ENV_SETTINGS \
144         "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
145         "nandboot=" \
146                 "nand read $(loadaddr) 0x0 0x900000;" \
147                 "run nandargs;" \
148                 "bootm" \
149                 "\0"
150
151 #endif