Merge git://git.denx.de/u-boot-nand-flash
[oweals/u-boot.git] / include / configs / pr1.h
1 /*
2  * U-Boot - Configuration file for PR1 Appliance
3  *
4  * based on bf537-stamp.h
5  * Copyright (c) Switchfin Org. <dpn@switchfin.org>
6  */
7
8 #ifndef __CONFIG_PR1_H__
9 #define __CONFIG_PR1_H__
10
11 #include <asm/config-pre.h>
12
13 /*
14  * Processor Settings
15  */
16 #define CONFIG_BFIN_CPU             bf537-0.3
17 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
18
19 /*
20  * Clock Settings
21  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
22  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
23  */
24 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
25 #define CONFIG_CLKIN_HZ                 25000000
26 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
27 /*                                                1 = CLKIN / 2         */
28 #define CONFIG_CLKIN_HALF               0
29 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
30 /*                                                1 = bypass PLL        */
31 #define CONFIG_PLL_BYPASS               0
32 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
33 /* Values can range from 0-63 (where 0 means 64)                        */
34 #define CONFIG_VCO_MULT                 24
35 /* CCLK_DIV controls the core clock divider                             */
36 /* Values can be 1, 2, 4, or 8 ONLY                                     */
37 #define CONFIG_CCLK_DIV                 1
38 /* SCLK_DIV controls the system clock divider                           */
39 /* Values can range from 1-15                                           */
40 #define CONFIG_SCLK_DIV                 5
41
42 /*
43  * Memory Settings
44  */
45 #define CONFIG_MEM_ADD_WDTH     11
46 #define CONFIG_MEM_SIZE         128
47
48 #define CONFIG_EBIU_SDRRC_VAL   0x306
49 #define CONFIG_EBIU_SDGCTL_VAL  0x8091998d
50
51 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
52 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
53 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
54
55 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
56 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)
57
58 /*
59  * Network Settings
60  */
61 #ifndef __ADSPBF534__
62 #define ADI_CMDS_NETWORK        1
63 #define CONFIG_BFIN_MAC
64 #define CONFIG_NETCONSOLE
65 #endif
66 #define CONFIG_HOSTNAME         pr1
67 #define CONFIG_TFTP_BLOCKSIZE   4404
68
69 /*
70  * Flash Settings
71  */
72 #define CONFIG_SYS_NO_FLASH     /* We have no parallel FLASH */
73
74 /*
75  * SPI Settings
76  */
77 #define CONFIG_BFIN_SPI
78 #define CONFIG_ENV_SPI_MAX_HZ   30000000
79 #define CONFIG_SF_DEFAULT_SPEED 30000000
80
81 /*
82  * Env Storage Settings
83  */
84 #define CONFIG_ENV_IS_IN_SPI_FLASH
85 #define CONFIG_ENV_OFFSET       0x10000
86 #define CONFIG_ENV_SIZE         0x2000
87 #define CONFIG_ENV_SECT_SIZE    0x10000
88 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
89
90 /*
91  * I2C Settings
92  */
93 #define CONFIG_SYS_I2C
94 #define CONFIG_SYS_I2C_ADI
95
96 /*
97  * NAND Settings
98  */
99 #define CONFIG_NAND_PLAT
100 #define CONFIG_SYS_NAND_BASE            0x20000000
101 #define CONFIG_SYS_MAX_NAND_DEVICE      1
102
103 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
104 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
105 #define BFIN_NAND_WRITE(addr, cmd) \
106         do { \
107                 bfin_write8(addr, cmd); \
108                 SSYNC(); \
109         } while (0)
110
111 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
112 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
113 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF9
114
115 /*
116  * Misc Settings
117  */
118 #define CONFIG_BAUDRATE         115200
119 #define CONFIG_RTC_BFIN
120 #define CONFIG_UART_CONSOLE     0
121 #define CONFIG_BOOTCOMMAND      "run nandboot"
122 #define CONFIG_LOADADDR         0x2000000
123
124 /*
125  * Pull in common ADI header for remaining command/environment setup
126  */
127 #include <configs/bfin_adi_common.h>
128
129 /*
130  * Overwrite some settings defined in bfin_adi_common.h
131  */
132 #undef NAND_ENV_SETTINGS
133 #define NAND_ENV_SETTINGS \
134         "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
135         "nandboot=" \
136                 "nand read $(loadaddr) 0x0 0x900000;" \
137                 "run nandargs;" \
138                 "bootm" \
139                 "\0"
140
141 #endif