ARMV7: AM3517/05: Add support for CraneBoard.
[oweals/u-boot.git] / include / configs / pm9261.h
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian.pop@leadtechdesign.com>
4  * Lead Tech Design <www.leadtechdesign.com>
5  * Ilko Iliev <www.ronetix.at>
6  *
7  * Configuation settings for the RONETIX PM9261 board.
8  *
9  * See file CREDITS for list of people who contributed to this
10  * project.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation; either version 2 of
15  * the License, or (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  */
27
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30
31 /* ARM asynchronous clock */
32 #define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9261"
33
34 #define CONFIG_DISPLAY_BOARDINFO
35
36 #define MASTER_PLL_DIV          15
37 #define MASTER_PLL_MUL          162
38 #define MAIN_PLL_DIV            2
39 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000
40
41 #define CONFIG_SYS_HZ           1000
42
43 #define CONFIG_ARM926EJS        1       /* This is an ARM926EJS Core    */
44 #define CONFIG_AT91SAM9261      1       /* It's an Atmel AT91SAM9261 SoC*/
45 #define CONFIG_PM9261           1       /* on a Ronetix PM9261 Board    */
46 #define CONFIG_ARCH_CPU_INIT
47 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff  */
48 #define CONFIG_SYS_TEXT_BASE    0
49 #define CONFIG_AT91FAMILY
50
51 /* clocks */
52 /* CKGR_MOR - enable main osc. */
53 #define CONFIG_SYS_MOR_VAL                                              \
54                 (AT91_PMC_MOR_MOSCEN |                                  \
55                  (255 << 8))            /* Main Oscillator Start-up Time */
56 #define CONFIG_SYS_PLLAR_VAL                                            \
57                 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
58                  AT91_PMC_PLLXR_OUT(3) |                                                \
59                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
60
61 /* PCK/2 = MCK Master Clock from PLLA */
62 #define CONFIG_SYS_MCKR1_VAL            \
63                 (AT91_PMC_MCKR_CSS_SLOW |       \
64                  AT91_PMC_MCKR_PRES_1 | \
65                  AT91_PMC_MCKR_MDIV_2 | \
66                  AT91_PMC_MCKR_PLLADIV_1)
67
68 /* PCK/2 = MCK Master Clock from PLLA */
69 #define CONFIG_SYS_MCKR2_VAL            \
70                 (AT91_PMC_MCKR_CSS_PLLA |       \
71                  AT91_PMC_MCKR_PRES_1 | \
72                  AT91_PMC_MCKR_MDIV_2 | \
73                  AT91_PMC_MCKR_PLLADIV_1)
74
75 /* define PDC[31:16] as DATA[31:16] */
76 #define CONFIG_SYS_PIOC_PDR_VAL1        0xFFFF0000
77 /* no pull-up for D[31:16] */
78 #define CONFIG_SYS_PIOC_PPUDR_VAL       0xFFFF0000
79
80 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
81 #define CONFIG_SYS_MATRIX_EBICSA_VAL            \
82         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
83
84 /* SDRAM */
85 /* SDRAMC_MR Mode register */
86 #define CONFIG_SYS_SDRC_MR_VAL1         AT91_SDRAMC_MODE_NORMAL
87 /* SDRAMC_TR - Refresh Timer register */
88 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
89 /* SDRAMC_CR - Configuration register*/
90 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
91                 (AT91_SDRAMC_NC_9 |                                             \
92                  AT91_SDRAMC_NR_13 |                                            \
93                  AT91_SDRAMC_NB_4 |                                             \
94                  AT91_SDRAMC_CAS_3 |                                            \
95                  AT91_SDRAMC_DBW_32 |                                           \
96                  (1 <<  8) |            /* Write Recovery Delay */              \
97                  (7 << 12) |            /* Row Cycle Delay */                   \
98                  (3 << 16) |            /* Row Precharge Delay */               \
99                  (2 << 20) |            /* Row to Column Delay */               \
100                  (5 << 24) |            /* Active to Precharge Delay */         \
101                  (1 << 28))             /* Exit Self Refresh to Active Delay */
102
103 /* Memory Device Register -> SDRAM */
104 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
105 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
106 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
107 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
108 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
109 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
110 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
111 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
112 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
113 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
114 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
115 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
116 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
117 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
118 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
119 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
120 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
121 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
122
123 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
124 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
125                 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
126                  AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
127 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
128                 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
129                  AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
130 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
131                 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
132 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
133                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
134                  AT91_SMC_MODE_DBW_16 |                         \
135                  AT91_SMC_MODE_TDF |                            \
136                  AT91_SMC_MODE_TDF_CYCLE(6))
137
138 /* user reset enable */
139 #define CONFIG_SYS_RSTC_RMR_VAL                 \
140                 (AT91_RSTC_KEY |                \
141                 AT91_RSTC_CR_PROCRST |          \
142                 AT91_RSTC_MR_ERSTL(1) | \
143                 AT91_RSTC_MR_ERSTL(2))
144
145 /* Disable Watchdog */
146 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
147                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
148                  AT91_WDT_MR_WDV(0xfff) |                                       \
149                  AT91_WDT_MR_WDDIS |                            \
150                  AT91_WDT_MR_WDD(0xfff))
151
152 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
153 #define CONFIG_SETUP_MEMORY_TAGS 1
154 #define CONFIG_INITRD_TAG       1
155
156 #undef CONFIG_SKIP_LOWLEVEL_INIT
157
158 /*
159  * Hardware drivers
160  */
161 #define CONFIG_AT91_GPIO        1
162 #define CONFIG_ATMEL_USART      1
163 #undef CONFIG_USART0
164 #undef CONFIG_USART1
165 #undef CONFIG_USART2
166 #define CONFIG_USART3           1       /* USART 3 is DBGU */
167
168 /* LCD */
169 #define CONFIG_LCD                      1
170 #define LCD_BPP                         LCD_COLOR8
171 #define CONFIG_LCD_LOGO                 1
172 #undef LCD_TEST_PATTERN
173 #define CONFIG_LCD_INFO                 1
174 #define CONFIG_LCD_INFO_BELOW_LOGO      1
175 #define CONFIG_SYS_WHITE_ON_BLACK       1
176 #define CONFIG_ATMEL_LCD                1
177 #define CONFIG_ATMEL_LCD_BGR555         1
178 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
179
180 /* LED */
181 #define CONFIG_AT91_LED
182 #define CONFIG_RED_LED          AT91_PIO_PORTC, 12
183 #define CONFIG_GREEN_LED        AT91_PIO_PORTC, 13
184 #define CONFIG_YELLOW_LED       AT91_PIO_PORTC, 15
185
186 #define CONFIG_BOOTDELAY        3
187
188 /*
189  * BOOTP options
190  */
191 #define CONFIG_BOOTP_BOOTFILESIZE       1
192 #define CONFIG_BOOTP_BOOTPATH           1
193 #define CONFIG_BOOTP_GATEWAY            1
194 #define CONFIG_BOOTP_HOSTNAME           1
195
196 /*
197  * Command line configuration.
198  */
199 #include <config_cmd_default.h>
200 #undef CONFIG_CMD_BDI
201 #undef CONFIG_CMD_IMI
202 #undef CONFIG_CMD_FPGA
203 #undef CONFIG_CMD_LOADS
204 #undef CONFIG_CMD_IMLS
205
206 #define CONFIG_CMD_CACHE
207 #define CONFIG_CMD_PING         1
208 #define CONFIG_CMD_DHCP         1
209 #define CONFIG_CMD_NAND         1
210 #define CONFIG_CMD_USB          1
211
212 /* SDRAM */
213 #define CONFIG_NR_DRAM_BANKS                    1
214 #define PHYS_SDRAM                              0x20000000
215 #define PHYS_SDRAM_SIZE                         0x04000000      /* 64 megs */
216
217 /* DataFlash */
218 #define CONFIG_ATMEL_DATAFLASH_SPI
219 #define CONFIG_HAS_DATAFLASH
220 #define CONFIG_SYS_SPI_WRITE_TOUT               (5 * CONFIG_SYS_HZ)
221 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          1
222 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* CS0 */
223 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3     0xD0000000      /* CS3 */
224 #define AT91_SPI_CLK                            15000000
225 #define DATAFLASH_TCSS                          (0x1a << 16)
226 #define DATAFLASH_TCHS                          (0x1 << 24)
227
228 /* NAND flash */
229 #define CONFIG_NAND_ATMEL
230 #define NAND_MAX_CHIPS                          1
231 #define CONFIG_SYS_MAX_NAND_DEVICE              1
232 #define CONFIG_SYS_NAND_BASE                    0x40000000
233 #define CONFIG_SYS_NAND_DBW_8                   1
234 /* our ALE is AD22 */
235 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 22)
236 /* our CLE is AD21 */
237 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 21)
238 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIO_PORTC, 14
239 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIO_PORTA, 16
240
241 /* NOR flash */
242 #define CONFIG_SYS_FLASH_CFI                    1
243 #define CONFIG_FLASH_CFI_DRIVER                 1
244 #define PHYS_FLASH_1                            0x10000000
245 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
246 #define CONFIG_SYS_MAX_FLASH_SECT               256
247 #define CONFIG_SYS_MAX_FLASH_BANKS              1
248
249 /* Ethernet */
250 #define CONFIG_DRIVER_DM9000                    1
251 #define CONFIG_DM9000_BASE                      0x30000000
252 #define DM9000_IO                               CONFIG_DM9000_BASE
253 #define DM9000_DATA                             (CONFIG_DM9000_BASE + 4)
254 #define CONFIG_DM9000_USE_16BIT                 1
255 #define CONFIG_NET_RETRY_COUNT                  20
256 #define CONFIG_RESET_PHY_R                      1
257 #define CONFIG_NET_MULTI
258
259 /* USB */
260 #define CONFIG_USB_ATMEL
261 #define CONFIG_USB_OHCI_NEW                     1
262 #define CONFIG_DOS_PARTITION                    1
263 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
264 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00500000
265 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9261"
266 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
267 #define CONFIG_USB_STORAGE                      1
268
269 #define CONFIG_SYS_LOAD_ADDR                    0x22000000
270
271 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
272 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
273
274 #undef CONFIG_SYS_USE_DATAFLASH_CS0
275 #undef CONFIG_SYS_USE_NANDFLASH
276 #define CONFIG_SYS_USE_FLASH    1
277
278 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
279
280 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
281 #define CONFIG_ENV_IS_IN_DATAFLASH      1
282 #define CONFIG_SYS_MONITOR_BASE         \
283                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
284 #define CONFIG_ENV_OFFSET       0x4200
285 #define CONFIG_ENV_ADDR         \
286                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
287 #define CONFIG_ENV_SIZE         0x4200
288 #define CONFIG_BOOTCOMMAND      "cp.b 0xC0042000 0x22000000 0x210000; bootm"
289 #define CONFIG_BOOTARGS         "console=ttyS0,115200 "                 \
290                                 "root=/dev/mtdblock0 "                  \
291                                 "mtdparts=atmel_nand:-(root) "          \
292                                 "rw rootfstype=jffs2"
293
294 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
295
296 /* bootstrap + u-boot + env + linux in nandflash */
297 #define CONFIG_ENV_IS_IN_NAND           1
298 #define CONFIG_ENV_OFFSET               0x60000
299 #define CONFIG_ENV_OFFSET_REDUND        0x80000
300 #define CONFIG_ENV_SIZE                 0x20000         /* 1 sector = 128 kB */
301 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0xA0000 0x200000; bootm"
302 #define CONFIG_BOOTARGS         "console=ttyS0,115200 "                 \
303                                 "root=/dev/mtdblock5 "                  \
304                                 "mtdparts=atmel_nand:128k(bootstrap)ro,"        \
305                                 "256k(uboot)ro,128k(env1)ro,"           \
306                                 "128k(env2)ro,2M(linux),-(root) "       \
307                                 "rw rootfstype=jffs2"
308
309 #elif defined (CONFIG_SYS_USE_FLASH)
310
311 #define CONFIG_ENV_IS_IN_FLASH  1
312 #define CONFIG_ENV_OFFSET       0x40000
313 #define CONFIG_ENV_SECT_SIZE    0x10000
314 #define CONFIG_ENV_SIZE         0x10000
315 #define CONFIG_ENV_OVERWRITE    1
316
317 /* JFFS Partition offset set */
318 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
319 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
320
321 /* 512k reserved for u-boot */
322 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   11
323
324 #define CONFIG_BOOTCOMMAND      "run flashboot"
325
326 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0,nand0=nand"
327 #define MTDPARTS_DEFAULT                \
328         "mtdparts=physmap-flash.0:"     \
329                 "256k(u-boot)ro,"       \
330                 "64k(u-boot-env)ro,"    \
331                 "1408k(kernel),"        \
332                 "-(rootfs);"            \
333         "nand:-(nand)"
334
335 #define CONFIG_CON_ROT "fbcon=rotate:3 "
336 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT
337
338 #define CONFIG_EXTRA_ENV_SETTINGS                               \
339         "mtdids=" MTDIDS_DEFAULT "\0"                           \
340         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
341         "partition=nand0,0\0"                                   \
342         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
343         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
344                 CONFIG_CON_ROT                                  \
345                 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
346         "addip=setenv bootargs $(bootargs) "                    \
347                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
348                 ":$(hostname):eth0:off\0"                       \
349         "ramboot=tftpboot 0x22000000 vmImage;"                  \
350                 "run ramargs;run addip;bootm 22000000\0"        \
351         "nfsboot=tftpboot 0x22000000 vmImage;"                  \
352                 "run nfsargs;run addip;bootm 22000000\0"        \
353         "flashboot=run ramargs;run addip;bootm 0x10050000\0"    \
354         ""
355 #else
356 #error "Undefined memory device"
357 #endif
358
359 #define CONFIG_BAUDRATE                 115200
360 #define CONFIG_SYS_BAUDRATE_TABLE       {115200 , 19200, 38400, 57600, 9600 }
361
362 #define CONFIG_SYS_PROMPT               "pm9261> "
363 #define CONFIG_SYS_CBSIZE               256
364 #define CONFIG_SYS_MAXARGS              16
365 #define CONFIG_SYS_PBSIZE               \
366                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
367 #define CONFIG_SYS_LONGHELP             1
368 #define CONFIG_CMDLINE_EDITING  1
369
370 /*
371  * Size of malloc() pool
372  */
373 #define CONFIG_SYS_MALLOC_LEN           \
374                 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
375
376 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
377 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
378                                 GENERATED_GBL_DATA_SIZE)
379
380 #define CONFIG_STACKSIZE                (32 * 1024)     /* regular stack */
381
382 #ifdef CONFIG_USE_IRQ
383 #error CONFIG_USE_IRQ not supported
384 #endif
385
386 #endif