1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017 NXP Semiconductors
5 * Configuration settings for the i.MX7D Pico board.
8 #ifndef __PICO_IMX7D_CONFIG_H
9 #define __PICO_IMX7D_CONFIG_H
11 #include "mx7_common.h"
15 /* Size of malloc() pool */
16 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
18 #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
21 #define CONFIG_FEC_MXC
23 #define CONFIG_FEC_XCV_TYPE RGMII
24 #define CONFIG_ETHPRIME "FEC"
25 #define CONFIG_FEC_MXC_PHYADDR 1
27 #define CONFIG_PHY_ATHEROS
30 #define IMX_FEC_BASE ENET_IPS_BASE_ADDR
33 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
35 #define CONFIG_DFU_ENV_SETTINGS \
37 "spl raw 0x2 0x400 mmcpart 1;" \
38 "u-boot raw 0x8a 0x400 mmcpart 1;" \
39 "/boot/zImage ext4 0 1;" \
40 "/boot/imx7d-pico-pi.dtb ext4 0 1;" \
43 #define BOOTMENU_ENV \
44 "bootmenu_0=Boot using PICO-PI baseboard=" \
45 "setenv fdtfile imx7d-pico-pi.dtb\0" \
47 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
48 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
50 #define CONFIG_EXTRA_ENV_SETTINGS \
54 "fdt_high=0xffffffff\0" \
55 "initrd_high=0xffffffff\0" \
58 "fdt_addr=0x83000000\0" \
59 "fdt_addr_r=0x83000000\0" \
60 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
61 "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
62 "ramdisk_addr_r=0x83000000\0" \
63 "ramdiskaddr=0x83000000\0" \
64 "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
65 CONFIG_DFU_ENV_SETTINGS \
67 "if test $fdtfile = ask ; then " \
69 "if test $fdtfile != ask ; then " \
71 "finduuid=part uuid mmc 0:1 uuid\0" \
73 "uuid_disk=${uuid_gpt_disk};" \
74 "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \
75 "fastboot_partition_alias_system=rootfs\0" \
76 "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \
79 #define BOOT_TARGET_DEVICES(func) \
83 #include <config_distro_bootcmd.h>
85 #define CONFIG_SYS_MEMTEST_START 0x80000000
86 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
88 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
89 #define CONFIG_SYS_HZ 1000
91 /* Physical Memory Map */
92 #define CONFIG_NR_DRAM_BANKS 1
93 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
95 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
96 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
97 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
99 #define CONFIG_SYS_INIT_SP_OFFSET \
100 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
101 #define CONFIG_SYS_INIT_SP_ADDR \
102 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
105 #define CONFIG_SYS_I2C
106 #define CONFIG_SYS_I2C_MXC
107 #define CONFIG_SYS_I2C_MXC_I2C1
108 #define CONFIG_SYS_I2C_MXC_I2C2
109 #define CONFIG_SYS_I2C_MXC_I2C3
110 #define CONFIG_SYS_I2C_MXC_I2C4
111 #define CONFIG_SYS_I2C_SPEED 100000
115 #define CONFIG_POWER_I2C
116 #define CONFIG_POWER_PFUZE3000
117 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
119 /* FLASH and environment organization */
120 #define CONFIG_ENV_SIZE SZ_8K
122 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
123 #define CONFIG_SYS_FSL_USDHC_NUM 2
125 #define CONFIG_SYS_MMC_ENV_DEV 0
126 #define CONFIG_SYS_MMC_ENV_PART 0
129 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
130 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
131 #define CONFIG_MXC_USB_FLAGS 0
132 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
134 #define CONFIG_IMX_THERMAL