2 * (C) Copyright 2006-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * Configuation settings for the PDNB3 board.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * High Level Configuration Options
33 #define CONFIG_IXP425 1 /* This is an IXP425 CPU */
34 #define CONFIG_PDNB3 1 /* on an PDNB3 board */
36 #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
37 #define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
42 #define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
43 #define CONFIG_NET_MULTI 1
44 #define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */
45 #define CONFIG_HAS_ETH1
46 #define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */
47 #define CONFIG_MII 1 /* MII PHY management */
48 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
51 * Misc configuration options
53 #define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
54 #define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
56 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
57 #define CONFIG_SETUP_MEMORY_TAGS 1
58 #define CONFIG_INITRD_TAG 1
61 * Size of malloc() pool
63 #define CONFIG_SYS_MALLOC_LEN (1 << 20)
65 /* allow to overwrite serial and ethaddr */
66 #define CONFIG_ENV_OVERWRITE
68 #define CONFIG_IXP_SERIAL
69 #define CONFIG_BAUDRATE 115200
70 #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
76 #define CONFIG_BOOTP_BOOTFILESIZE
77 #define CONFIG_BOOTP_BOOTPATH
78 #define CONFIG_BOOTP_GATEWAY
79 #define CONFIG_BOOTP_HOSTNAME
83 * Command line configuration.
85 #include <config_cmd_default.h>
87 #define CONFIG_CMD_DHCP
88 #define CONFIG_CMD_DATE
89 #define CONFIG_CMD_NET
90 #define CONFIG_CMD_MII
91 #define CONFIG_CMD_I2C
92 #define CONFIG_CMD_ELF
93 #define CONFIG_CMD_PING
95 #if !defined(CONFIG_SCPU)
96 #define CONFIG_CMD_NAND
100 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
101 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
104 * Miscellaneous configurable options
106 #define CONFIG_SYS_LONGHELP /* undef to save memory */
107 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
108 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
109 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
110 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
111 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
113 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
114 #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
115 #define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
117 #define CONFIG_IXP425_TIMER_CLK 66666666
118 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
119 /* valid baudrates */
120 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
125 * The stack sizes are set up in start.S using the settings below
127 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
128 #ifdef CONFIG_USE_IRQ
129 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
130 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
133 /***************************************************************
134 * Platform/Board specific defines start here.
135 ***************************************************************/
137 /*-----------------------------------------------------------------------
138 * Default configuration (environment varibles...)
139 *----------------------------------------------------------------------*/
140 #define CONFIG_PREBOOT "echo;" \
141 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
144 #undef CONFIG_BOOTARGS
146 #define CONFIG_EXTRA_ENV_SETTINGS \
149 "nfsargs=setenv bootargs root=/dev/nfs rw " \
150 "nfsroot=${serverip}:${rootpath}\0" \
151 "ramargs=setenv bootargs root=/dev/ram rw\0" \
152 "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
153 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
154 ":${hostname}:${netdev}:off panic=1\0" \
155 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \
156 "mtdparts=${mtdparts}\0" \
157 "flash_nfs=run nfsargs addip addtty;" \
158 "bootm ${kernel_addr}\0" \
159 "flash_self=run ramargs addip addtty;" \
160 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
161 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
163 "rootpath=/opt/buildroot\0" \
164 "bootfile=/tftpboot/netbox/uImage\0" \
165 "kernel_addr=50080000\0" \
166 "ramdisk_addr=50200000\0" \
167 "load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \
168 "update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \
169 "cp.b 100000 50000000 ${filesize};" \
170 "setenv filesize;saveenv\0" \
171 "upd=run load update\0" \
172 "ipaddr=10.0.0.233\0" \
173 "serverip=10.0.0.152\0" \
174 "netmask=255.255.0.0\0" \
175 "ethaddr=c6:6f:13:36:f3:81\0" \
176 "eth1addr=c6:6f:13:36:f3:82\0" \
177 "mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \
180 #define CONFIG_BOOTCOMMAND "run net_nfs"
183 * Physical Memory Map
185 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
186 #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
187 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
189 #define CONFIG_SYS_TEXT_BASE 0x50000000
190 #define CONFIG_SYS_FLASH_BASE 0x50000000
191 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
192 #if defined(CONFIG_SCPU)
193 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */
195 #define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */
199 * Expansion bus settings
201 #if defined(CONFIG_SCPU)
202 #define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size */
204 #define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size */
206 #define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes */
211 #define CONFIG_SYS_SDR_CONFIG 0x18
212 #define CONFIG_SYS_SDR_MODE_CONFIG 0x1
213 #define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
216 * FLASH and environment organization
218 #if defined(CONFIG_SCPU)
219 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
220 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
221 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
224 #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
226 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
227 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
229 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
230 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
232 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
233 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
234 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
236 * The following defines are added for buggy IOP480 byte interface.
237 * All other boards should use the standard values (CPCI405 etc.)
239 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
240 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
241 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
243 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
245 #define CONFIG_ENV_IS_IN_FLASH 1
247 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
248 #if defined(CONFIG_SCPU)
249 /* no redundant environment on SCPU */
250 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
251 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
253 #define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
254 #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
256 /* Address and size of Redundant Environment Sector */
257 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
258 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
261 #if !defined(CONFIG_SCPU)
265 #define CONFIG_SYS_MAX_NAND_DEVICE 1
266 #define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
273 /* FPGA program pin configuration */
274 #define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin (cpu output)*/
275 #define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu output) */
276 #define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu output) */
277 #define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu input) */
278 #define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu input) */
281 #define CONFIG_SYS_GPIO_RESTORE_INT 0
282 #define CONFIG_SYS_GPIO_RESTART_INT 1
283 #define CONFIG_SYS_GPIO_SYS_RUNNING 2
284 #define CONFIG_SYS_GPIO_PCI_INTA 3
285 #define CONFIG_SYS_GPIO_PCI_INTB 4
286 #define CONFIG_SYS_GPIO_I2C_SCL 6
287 #define CONFIG_SYS_GPIO_I2C_SDA 7
288 #define CONFIG_SYS_GPIO_FPGA_RESET 9
289 #define CONFIG_SYS_GPIO_CLK_33M 15
295 /* enable I2C and select the hardware/software driver */
296 #undef CONFIG_HARD_I2C /* I2C with hardware support */
297 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
299 #define CONFIG_SYS_I2C_SPEED 83000 /* 83 kHz is supposed to work */
300 #define CONFIG_SYS_I2C_SLAVE 0xFE
303 * Software (bit-bang) I2C driver configuration
305 #define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL)
306 #define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA)
308 #define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL)
309 #define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA)
310 #define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA)
311 #define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0)
312 #define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \
313 else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA)
314 #define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \
315 else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL)
316 #define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
321 #if 0 /* test-only */
322 #define CONFIG_RTC_DS1340 1
323 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
325 /* M41T11 Serial Access Timekeeper(R) SRAM */
326 #define CONFIG_RTC_M41T11 1
327 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
328 #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
332 * Spartan3 FPGA configuration support
334 #define CONFIG_SYS_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */
336 #define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program pin (cpu output)*/
337 #define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin (cpu output) */
338 #define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data pin (cpu output) */
339 #define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init pin (cpu input) */
340 #define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done pin (cpu input) */
343 * Cache Configuration
345 #define CONFIG_SYS_CACHELINE_SIZE 32
347 /* additions for new relocation code, must be added to all boards */
348 #define CONFIG_SYS_SDRAM_BASE 0x00000000
349 #define CONFIG_SYS_INIT_SP_ADDR \
350 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
352 #endif /* __CONFIG_H */