2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * Workaround for layout bug on prototype board
34 #define PCU_E_WITH_SWAPPED_CS 1
37 * High Level Configuration Options
41 #define CONFIG_MPC860 1 /* This is a MPC860T CPU */
42 #define CONFIG_MPC860T 1
43 #define CONFIG_PCU_E 1 /* ...on a PCU E board */
45 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
47 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
49 #define CONFIG_BAUDRATE 9600
51 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
53 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
56 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
58 #undef CONFIG_BOOTARGS
59 #define CONFIG_BOOTCOMMAND \
61 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
62 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
65 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
66 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
68 #undef CONFIG_WATCHDOG /* watchdog disabled */
70 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
72 #define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
74 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
76 #define CONFIG_SPI /* enable SPI driver */
77 #define CONFIG_SPI_X /* 16 bit EEPROM addressing */
79 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
80 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
81 #define CONFIG_SYS_I2C_SLAVE 0x7F
84 /* ----------------------------------------------------------------
85 * Offset to initial SPI buffers in DPRAM (used if the environment
86 * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
87 * use at an early stage. It is used between the two initialization
88 * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
89 * far enough from the start of the data area (as well as from the
91 * ---------------------------------------------------------------- */
92 #define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
96 * Command line configuration.
98 #include <config_cmd_default.h>
99 #define CONFIG_CMD_BSP
100 #define CONFIG_CMD_DATE
101 #define CONFIG_CMD_DHCP
102 #define CONFIG_CMD_EEPROM
103 #define CONFIG_CMD_NFS
104 #define CONFIG_CMD_SNTP
110 #define CONFIG_BOOTP_SUBNETMASK
111 #define CONFIG_BOOTP_HOSTNAME
112 #define CONFIG_BOOTP_BOOTPATH
113 #define CONFIG_BOOTP_BOOTFILESIZE
117 * Miscellaneous configurable options
119 #define CONFIG_SYS_LONGHELP /* undef to save memory */
120 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
121 #if defined(CONFIG_CMD_KGDB)
122 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
124 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
126 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
127 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
128 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
130 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
131 #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
133 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
135 #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
137 /* Ethernet hardware configuration done using port pins */
138 #define CONFIG_SYS_PB_ETH_RESET 0x00000020 /* PB 26 */
139 #if PCU_E_WITH_SWAPPED_CS /* XXX */
140 #define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */
141 #define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
142 #define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */
143 #define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */
144 #define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */
146 #define CONFIG_SYS_PB_ETH_MDDIS 0x00000010 /* PB 27 */
147 #define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */
148 #define CONFIG_SYS_PB_ETH_CFG1 0x00000200 /* PB 22 */
149 #define CONFIG_SYS_PB_ETH_CFG2 0x00000400 /* PB 21 */
150 #define CONFIG_SYS_PB_ETH_CFG3 0x00000800 /* PB 20 */
153 /* Ethernet settings:
154 * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
156 #define CONFIG_SYS_ETH_MDDIS_VALUE 0
157 #define CONFIG_SYS_ETH_CFG1_VALUE 1
158 #define CONFIG_SYS_ETH_CFG2_VALUE 1
159 #define CONFIG_SYS_ETH_CFG3_VALUE 1
161 /* PUMA configuration */
162 #if PCU_E_WITH_SWAPPED_CS /* XXX */
163 #define CONFIG_SYS_PB_PUMA_PROG 0x00000010 /* PB 27 */
165 #define CONFIG_SYS_PA_PUMA_PROG 0x4000 /* PA 1 */
167 #define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */
168 #define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */
170 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
172 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
175 * Low Level Configuration Settings
176 * (address mappings, register initial values, etc.)
177 * You should know what you are doing if you make changes here.
179 /*-----------------------------------------------------------------------
180 * Internal Memory Mapped Register
182 #define CONFIG_SYS_IMMR 0xFE000000
184 /*-----------------------------------------------------------------------
185 * Definitions for initial stack pointer and data area (in DPRAM)
187 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
188 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
189 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
190 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
191 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
193 /*-----------------------------------------------------------------------
194 * Address accessed to reset the board - must not be mapped/assigned
196 #define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF
198 /*-----------------------------------------------------------------------
199 * Start addresses for the final memory configuration
200 * (Set up by the startup code)
201 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
203 #define CONFIG_SYS_SDRAM_BASE 0x00000000
204 /* this is an ugly hack needed because of the silly non-constant address map */
205 #define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size-flash_info[1].size)
208 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
210 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
212 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
213 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
216 * For booting Linux, the board info and command line data
217 * have to be in the first 8 MB of memory, since this is
218 * the maximum mapped by the Linux kernel during initialization.
220 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
221 /*-----------------------------------------------------------------------
224 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
225 #define CONFIG_SYS_MAX_FLASH_SECT 160 /* max number of sectors on one chip */
227 #define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
228 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
231 /* Start port with environment in flash; switch to SPI EEPROM later */
232 #define CONFIG_ENV_IS_IN_FLASH 1
233 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */
234 #define CONFIG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */
235 #define CONFIG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */
237 /* Final version: environment in EEPROM */
238 #define CONFIG_ENV_IS_IN_EEPROM 1
239 #define CONFIG_SYS_I2C_EEPROM_ADDR 0
240 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
241 #define CONFIG_ENV_OFFSET 1024
242 #define CONFIG_ENV_SIZE 1024
245 /*-----------------------------------------------------------------------
246 * Cache Configuration
248 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
249 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
250 #define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
254 /*-----------------------------------------------------------------------
255 * SYPCR - System Protection Control 11-9
256 * SYPCR can only be written once after reset!
257 *-----------------------------------------------------------------------
258 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
260 #if defined(CONFIG_WATCHDOG)
261 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
262 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
264 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
267 /*-----------------------------------------------------------------------
268 * SIUMCR - SIU Module Configuration 11-6
269 *-----------------------------------------------------------------------
270 * External Arbitration max. priority (7),
271 * Debug pins configuration '11',
272 * Asynchronous external master enable.
275 #define CONFIG_SYS_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
277 /*-----------------------------------------------------------------------
278 * TBSCR - Time Base Status and Control 11-26
279 *-----------------------------------------------------------------------
280 * Clear Reference Interrupt Status, Timebase freezing enabled
282 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
284 /*-----------------------------------------------------------------------
285 * PISCR - Periodic Interrupt Status and Control 11-31
286 *-----------------------------------------------------------------------
287 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
289 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
291 /*-----------------------------------------------------------------------
292 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
293 *-----------------------------------------------------------------------
294 * Reset PLL lock status sticky bit, timer expired status bit and timer
295 * interrupt status bit, set PLL multiplication factor !
298 #define CONFIG_SYS_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */
299 #define CONFIG_SYS_PLPRCR \
300 ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
301 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
302 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
303 PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
306 #define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*50000000)
308 /*-----------------------------------------------------------------------
309 * SCCR - System Clock and reset Control Register 15-27
310 *-----------------------------------------------------------------------
311 * Set clock output, timebase and RTC source and divider,
312 * power management and some other internal clocks
314 * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz
316 #define SCCR_MASK SCCR_EBDF11
318 #define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
319 SCCR_RTDIV | SCCR_RTSEL | \
320 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
321 SCCR_EBDF00 | SCCR_DFSYNC00 | \
322 SCCR_DFBRG00 | SCCR_DFNL000 | \
323 SCCR_DFNH000 | SCCR_DFLCD100 | \
326 /*-----------------------------------------------------------------------
327 * RTCSC - Real-Time Clock Status and Control Register 11-27
328 *-----------------------------------------------------------------------
330 * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!!
332 * Don't expect the "date" command to work without a 32kHz clock input!
334 /* 0x00C3 => 0x0003 */
335 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
338 /*-----------------------------------------------------------------------
339 * RCCR - RISC Controller Configuration Register 19-4
340 *-----------------------------------------------------------------------
342 #define CONFIG_SYS_RCCR 0x0000
344 /*-----------------------------------------------------------------------
345 * RMDS - RISC Microcode Development Support Control Register
346 *-----------------------------------------------------------------------
348 #define CONFIG_SYS_RMDS 0
350 /*-----------------------------------------------------------------------
353 *-----------------------------------------------------------------------
355 #define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
357 /*-----------------------------------------------------------------------
359 *-----------------------------------------------------------------------
362 #define CONFIG_SYS_DER 0
365 * Init Memory Controller:
367 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
370 #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
371 #if PCU_E_WITH_SWAPPED_CS /* XXX */
372 #define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */
374 #define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */
378 * used to re-map FLASH: restrict access enough but not too much to
379 * meddle with FLASH accesses
381 #define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
382 #define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
384 /* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */
385 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR)
387 #define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
388 CONFIG_SYS_OR_TIMING_FLASH)
389 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
390 CONFIG_SYS_OR_TIMING_FLASH)
391 /* 16 bit, bank valid */
392 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
394 #if PCU_E_WITH_SWAPPED_CS /* XXX */
395 #define CONFIG_SYS_OR6_REMAP CONFIG_SYS_OR0_REMAP
396 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR0_PRELIM
397 #define CONFIG_SYS_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
399 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
400 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
401 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
407 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
409 #if PCU_E_WITH_SWAPPED_CS /* XXX */
410 #define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */
412 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */
414 #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */
415 #define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */
417 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
419 #if PCU_E_WITH_SWAPPED_CS /* XXX */
420 #define CONFIG_SYS_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
421 #define CONFIG_SYS_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
423 #define CONFIG_SYS_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
424 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
428 * BR3/OR3: CAN Controller
429 * BR3: 0x10000401 OR3: 0xffff818a
431 #define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */
432 #define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */
433 #define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
435 #if PCU_E_WITH_SWAPPED_CS /* XXX */
436 #define CONFIG_SYS_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
437 #define CONFIG_SYS_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
439 #define CONFIG_SYS_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
440 #define CONFIG_SYS_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
444 * BR4/OR4: PUMA Config
446 * Memory controller will be used in 2 modes:
449 * BR4: 0x10100801 OR4: 0xffff8530
450 * - "load" mode (chip select on UPM B):
451 * BR4: 0x101008c1 OR4: 0xffff8630
453 * Default initialization is in "read" mode
455 #define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
456 #define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
457 #define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK)
458 #define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK)
460 #define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
461 BR_PS_16 | BR_MS_UPMB | BR_V)
462 #define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
464 #define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
465 #define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
467 #if PCU_E_WITH_SWAPPED_CS /* XXX */
468 #define CONFIG_SYS_BR3_PRELIM PUMA_CONF_BR_READ
469 #define CONFIG_SYS_OR3_PRELIM PUMA_CONF_OR_READ
471 #define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ
472 #define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ
476 * BR5/OR5: PUMA: SMA Bus 8 Bit
477 * BR5: 0x10200401 OR5: 0xffe0010a
479 #define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
480 #define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
481 #define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
483 #if PCU_E_WITH_SWAPPED_CS /* XXX */
484 #define CONFIG_SYS_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
485 #define CONFIG_SYS_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
487 #define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
488 #define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
492 * BR6/OR6: PUMA: SMA Bus 16 Bit
493 * BR6: 0x10600801 OR6: 0xffe0010a
495 #define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
496 #define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
497 #define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
499 #if PCU_E_WITH_SWAPPED_CS /* XXX */
500 #define CONFIG_SYS_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
501 #define CONFIG_SYS_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
503 #define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
504 #define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
508 * BR7/OR7: PUMA: external Flash
509 * BR7: 0x10a00801 OR7: 0xfe00010a
511 #define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
512 #define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
513 #define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
515 #define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
516 #define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
519 * Memory Periodic Timer Prescaler
522 /* periodic timer for refresh */
523 #define CONFIG_SYS_MPTPR 0x0200
526 * MAMR settings for SDRAM
527 * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
528 * MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X
529 * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
531 /* periodic timer for refresh */
532 #define CONFIG_SYS_MAMR_PTA 0x30 /* = 48 */
534 #define CONFIG_SYS_MAMR ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \
542 * Internal Definitions
546 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
547 #define BOOTFLAG_WARM 0x02 /* Software reboot */
549 #endif /* __CONFIG_H */