2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * Configuration settings for the phytec PCM-052 SoM.
6 * SPDX-License-Identifier: GPL-2.0+
12 #define CONFIG_SYS_CACHELINE_SIZE 32
14 #include <asm/arch/imx-regs.h>
18 #define CONFIG_DISPLAY_CPUINFO
19 #define CONFIG_DISPLAY_BOARDINFO
20 #define CONFIG_SYS_THUMB_BUILD
22 #define CONFIG_SKIP_LOWLEVEL_INIT
24 /* Enable passing of ATAGs */
25 #define CONFIG_CMDLINE_TAG
27 /* Size of malloc() pool */
28 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
30 #define CONFIG_BOARD_EARLY_INIT_F
32 /* Allow to overwrite serial and ethaddr */
33 #define CONFIG_ENV_OVERWRITE
34 #define CONFIG_BAUDRATE 115200
37 #define CONFIG_CMD_NAND
38 #define CONFIG_CMD_NAND_TRIMFFS
39 #define CONFIG_SYS_NAND_ONFI_DETECTION
41 #ifdef CONFIG_CMD_NAND
42 #define CONFIG_USE_ARCH_MEMCPY
43 #define CONFIG_SYS_MAX_NAND_DEVICE 1
44 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
46 #define CONFIG_JFFS2_NAND
49 #define CONFIG_CMD_UBI
50 #define CONFIG_CMD_UBIFS
54 /* Dynamic MTD partition support */
55 #define CONFIG_CMD_MTDPARTS
56 #define CONFIG_MTD_PARTITIONS
57 #define CONFIG_MTD_DEVICE
58 #define MTDIDS_DEFAULT "nand0=NAND"
59 #define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\
70 #define CONFIG_FSL_ESDHC
71 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
72 #define CONFIG_SYS_FSL_ESDHC_NUM 1
74 /*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
75 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
76 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
77 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
79 #define CONFIG_GENERIC_MMC
80 #define CONFIG_DOS_PARTITION
82 #define CONFIG_FEC_MXC
84 #define IMX_FEC_BASE ENET_BASE_ADDR
85 #define CONFIG_FEC_XCV_TYPE RMII
86 #define CONFIG_FEC_MXC_PHYADDR 0
88 #define CONFIG_PHY_MICREL
92 #ifdef CONFIG_FSL_QSPI
93 #define CONFIG_SPI_FLASH
94 #define FSL_QSPI_FLASH_SIZE (1 << 24)
95 #define FSL_QSPI_FLASH_NUM 2
96 #define CONFIG_SYS_FSL_QSPI_LE
100 #define CONFIG_SYS_I2C
101 #define CONFIG_SYS_I2C_MXC_I2C3
102 #define CONFIG_SYS_I2C_MXC
104 /* RTC (actually an RV-4162 but M41T62-compatible) */
105 #define CONFIG_CMD_DATE
106 #define CONFIG_RTC_M41T62
107 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
108 #define CONFIG_SYS_RTC_BUS_NUM 2
110 /* EEPROM (24FC256) */
111 #define CONFIG_CMD_EEPROM
112 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
113 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
114 #define CONFIG_SYS_I2C_EEPROM_BUS 2
116 #define CONFIG_BOOTDELAY 3
118 #define CONFIG_LOADADDR 0x82000000
120 /* We boot from the gfxRAM area of the OCRAM. */
121 #define CONFIG_SYS_TEXT_BASE 0x3f408000
122 #define CONFIG_BOARD_SIZE_LIMIT 524288
124 #define CONFIG_BOOTCOMMAND "run bootcmd_sd"
125 #define CONFIG_EXTRA_ENV_SETTINGS \
126 "fdt_high=0xffffffff\0" \
127 "initrd_high=0xffffffff\0" \
128 "blimg_file=u-boot.imx\0" \
129 "blsec_addr=0x81000000\0" \
130 "blimg_addr=0x81000400\0" \
131 "kernel_file=zImage\0" \
132 "kernel_addr=0x82000000\0" \
133 "fdt_file=vf610-pcm052.dtb\0" \
134 "fdt_addr=0x81000000\0" \
135 "ram_file=uRamdisk\0" \
136 "ram_addr=0x83000000\0" \
137 "filesys=rootfs.ubifs\0" \
138 "sys_addr=0x81000000\0" \
139 "tftploc=/path/to/tftp/directory/\0" \
140 "nfs_root=/path/to/nfs/root\0" \
141 "tftptimeout=1000\0" \
142 "tftptimeoutcountmax=1000000\0" \
143 "mtdparts=" MTDPARTS_DEFAULT "\0" \
144 "bootargs_base=setenv bootargs rw mem=256M " \
145 "console=ttyLP1,115200n8\0" \
146 "bootargs_sd=setenv bootargs ${bootargs} " \
147 "root=/dev/mmcblk0p2 rootwait\0" \
148 "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
149 "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
150 "bootargs_nand=setenv bootargs ${bootargs} " \
151 "ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \
152 "bootargs_ram=setenv bootargs ${bootargs} " \
153 "root=/dev/ram rw initrd=${ram_addr}\0" \
154 "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
155 "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
156 "fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \
157 "fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \
158 "bootz ${kernel_addr} - ${fdt_addr}\0" \
159 "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
160 "tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \
161 "tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \
162 "bootz ${kernel_addr} - ${fdt_addr}\0" \
163 "bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \
164 "nand read ${fdt_addr} dtb; " \
165 "nand read ${kernel_addr} kernel; " \
166 "bootz ${kernel_addr} - ${fdt_addr}\0" \
167 "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
168 "nand read ${fdt_addr} dtb; " \
169 "nand read ${kernel_addr} kernel; " \
170 "nand read ${ram_addr} ramdisk; " \
171 "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
172 "update_bootloader_from_tftp=mtdparts default; " \
173 "nand read ${blsec_addr} bootloader; " \
174 "mw.b ${blimg_addr} 0xff 0x5FC00; " \
175 "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \
176 "nand erase.part bootloader; " \
177 "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \
178 "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
180 "then mtdparts default; " \
181 "nand erase.part kernel; " \
182 "nand write ${kernel_addr} kernel ${filesize}; " \
183 "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
184 "nand erase.part dtb; " \
185 "nand write ${fdt_addr} dtb ${filesize}; fi\0" \
186 "update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
187 "then setenv fdtsize ${filesize}; " \
188 "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
189 "mtdparts default; " \
190 "nand erase.part dtb; " \
191 "nand write ${fdt_addr} dtb ${fdtsize}; " \
192 "nand erase.part kernel; " \
193 "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
194 "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \
195 "then mtdparts default; " \
196 "nand erase.part root; " \
198 "ubi create rootfs; " \
199 "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
200 "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
201 "then mtdparts default; " \
202 "nand erase.part ramdisk; " \
203 "nand write ${ram_addr} ramdisk ${filesize}; fi\0"
205 /* Miscellaneous configurable options */
206 #define CONFIG_SYS_LONGHELP /* undef to save memory */
207 #define CONFIG_AUTO_COMPLETE
208 #define CONFIG_CMDLINE_EDITING
209 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
210 #define CONFIG_SYS_PBSIZE \
211 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
212 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
213 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
215 #define CONFIG_SYS_MEMTEST_START 0x80010000
216 #define CONFIG_SYS_MEMTEST_END 0x87C00000
218 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
222 * The stack sizes are set up in start.S using the settings below
224 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
226 /* Physical memory map */
227 #define CONFIG_NR_DRAM_BANKS 1
228 #define PHYS_SDRAM (0x80000000)
229 #define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
231 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
232 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
233 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
235 #define CONFIG_SYS_INIT_SP_OFFSET \
236 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
237 #define CONFIG_SYS_INIT_SP_ADDR \
238 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
240 /* FLASH and environment organization */
241 #define CONFIG_SYS_NO_FLASH
243 #ifdef CONFIG_ENV_IS_IN_MMC
244 #define CONFIG_ENV_SIZE (8 * 1024)
246 #define CONFIG_ENV_OFFSET (12 * 64 * 1024)
247 #define CONFIG_SYS_MMC_ENV_DEV 0
250 #ifdef CONFIG_ENV_IS_IN_NAND
251 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
252 #define CONFIG_ENV_SIZE (8 * 1024)
253 #define CONFIG_ENV_OFFSET 0xA0000
254 #define CONFIG_ENV_SIZE_REDUND (8 * 1024)
255 #define CONFIG_ENV_OFFSET_REDUND 0xC0000