2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * QorIQ P1 Tower boards configuration file
29 #if defined(CONFIG_TWR_P1025)
30 #define CONFIG_BOARDNAME "TWR-P1025"
32 #define CONFIG_PHY_ATHEROS
34 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
35 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
39 #define CONFIG_RAMBOOT_SDCARD
40 #define CONFIG_SYS_RAMBOOT
41 #define CONFIG_SYS_EXTRA_ENV_RELOC
42 #define CONFIG_SYS_TEXT_BASE 0x11000000
43 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
46 #ifndef CONFIG_SYS_TEXT_BASE
47 #define CONFIG_SYS_TEXT_BASE 0xeff80000
50 #ifndef CONFIG_RESET_VECTOR_ADDRESS
51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
54 #ifndef CONFIG_SYS_MONITOR_BASE
55 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
58 /* High Level Configuration Options */
61 #define CONFIG_MPC85xx
65 #define CONFIG_FSL_ELBC
67 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
68 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
69 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
70 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
71 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
72 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
74 #define CONFIG_FSL_LAW
75 #define CONFIG_TSEC_ENET /* tsec ethernet support */
76 #define CONFIG_ENV_OVERWRITE
78 #define CONFIG_CMD_SATA
79 #define CONFIG_SATA_SIL3114
80 #define CONFIG_SYS_SATA_MAX_DEVICE 2
85 extern unsigned long get_board_sys_clk(unsigned long dummy);
87 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */
89 #define CONFIG_DDR_CLK_FREQ 66666666
91 #define CONFIG_HWCONFIG
93 * These can be toggled for performance analysis, otherwise use default.
95 #define CONFIG_L2_CACHE
98 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
100 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
101 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
102 #define CONFIG_PANIC_HANG /* do not reset board on panic */
104 #define CONFIG_SYS_CCSRBAR 0xffe00000
105 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
108 #define CONFIG_FSL_DDR3
110 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
111 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
113 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
114 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
117 #define CONFIG_NUM_DDR_CONTROLLERS 1
118 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
120 /* Default settings for DDR3 */
121 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
122 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
123 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
124 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
125 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
126 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
128 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
129 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
130 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
131 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
133 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
134 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
135 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
136 #define CONFIG_SYS_DDR_RCW_1 0x00000000
137 #define CONFIG_SYS_DDR_RCW_2 0x00000000
138 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
139 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
140 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
141 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
143 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
144 #define CONFIG_SYS_DDR_TIMING_0 0x00220004
145 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
146 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
147 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
148 #define CONFIG_SYS_DDR_MODE_1 0x80461320
149 #define CONFIG_SYS_DDR_MODE_2 0x00008000
150 #define CONFIG_SYS_DDR_INTERVAL 0x09480000
155 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
156 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
157 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
160 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
161 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
163 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
164 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
165 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
169 * Local Bus Definitions
171 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
172 #define CONFIG_SYS_FLASH_BASE 0xec000000
174 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
176 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
179 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
181 #define CONFIG_SYS_SSD_BASE 0xe0000000
182 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
183 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
185 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
186 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
187 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
189 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
190 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
192 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
193 #define CONFIG_SYS_FLASH_QUIET_TEST
194 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
196 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
198 #undef CONFIG_SYS_FLASH_CHECKSUM
199 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
200 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
202 #define CONFIG_FLASH_CFI_DRIVER
203 #define CONFIG_SYS_FLASH_CFI
204 #define CONFIG_SYS_FLASH_EMPTY_INFO
205 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
207 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
209 #define CONFIG_SYS_INIT_RAM_LOCK
210 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
211 /* Initial L1 address */
212 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
213 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
214 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
215 /* Size of used area in RAM */
216 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
218 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
219 GENERATED_GBL_DATA_SIZE)
220 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
222 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)/* Reserve 512 kB for Mon */
223 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
225 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
226 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
232 #define CONFIG_CONS_INDEX 1
233 #undef CONFIG_SERIAL_SOFTWARE_FIFO
234 #define CONFIG_SYS_NS16550
235 #define CONFIG_SYS_NS16550_SERIAL
236 #define CONFIG_SYS_NS16550_REG_SIZE 1
237 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
239 #define CONFIG_SYS_BAUDRATE_TABLE \
240 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
242 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
243 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
245 /* Use the HUSH parser */
246 #define CONFIG_SYS_HUSH_PARSER
247 #ifdef CONFIG_SYS_HUSH_PARSER
248 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
252 * Pass open firmware flat tree
254 #define CONFIG_OF_LIBFDT
255 #define CONFIG_OF_BOARD_SETUP
256 #define CONFIG_OF_STDOUT_VIA_ALIAS
258 #define CONFIG_SYS_64BIT_VSPRINTF
259 #define CONFIG_SYS_64BIT_STRTOUL
261 /* new uImage format support */
263 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
266 #define CONFIG_SYS_I2C
267 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
268 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
269 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
270 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
271 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
276 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
277 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
278 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
280 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
282 /* enable read and write access to EEPROM */
283 #define CONFIG_CMD_EEPROM
284 #define CONFIG_SYS_I2C_MULTI_EEPROMS
285 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
286 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
287 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
290 * eSPI - Enhanced SPI
292 #define CONFIG_HARD_SPI
293 #define CONFIG_FSL_ESPI
295 #if defined(CONFIG_PCI)
298 * Memory space is mapped 1-1, but I/O space must start from 0.
301 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
302 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
303 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
304 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
305 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
306 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
307 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
308 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
309 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
310 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
312 /* controller 1, tgtid 1, Base address a000 */
313 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
314 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
315 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
316 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
317 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
318 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
319 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
320 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
321 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
323 #define CONFIG_NET_MULTI
324 #define CONFIG_PCI_PNP /* do pci plug-and-play */
325 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
326 #define CONFIG_CMD_PCI
327 #define CONFIG_CMD_NET
329 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
330 #define CONFIG_DOS_PARTITION
331 #endif /* CONFIG_PCI */
333 #if defined(CONFIG_TSEC_ENET)
335 #ifndef CONFIG_NET_MULTI
336 #define CONFIG_NET_MULTI
339 #define CONFIG_MII /* MII PHY management */
341 #define CONFIG_TSEC1_NAME "eTSEC1"
343 #undef CONFIG_TSEC2_NAME
345 #define CONFIG_TSEC3_NAME "eTSEC3"
347 #define TSEC1_PHY_ADDR 2
348 #define TSEC2_PHY_ADDR 0
349 #define TSEC3_PHY_ADDR 1
351 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
352 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
353 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
355 #define TSEC1_PHYIDX 0
356 #define TSEC2_PHYIDX 0
357 #define TSEC3_PHYIDX 0
359 #define CONFIG_ETHPRIME "eTSEC1"
361 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
363 #define CONFIG_HAS_ETH0
364 #define CONFIG_HAS_ETH1
365 #undef CONFIG_HAS_ETH2
366 #endif /* CONFIG_TSEC_ENET */
369 /* QE microcode/firmware address */
370 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
371 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000
372 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
373 #endif /* CONFIG_QE */
375 #ifdef CONFIG_TWR_P1025
377 * QE UEC ethernet configuration
379 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
381 #undef CONFIG_UEC_ETH
382 #define CONFIG_PHY_MODE_NEED_CHANGE
384 #define CONFIG_UEC_ETH1 /* ETH1 */
385 #define CONFIG_HAS_ETH0
387 #ifdef CONFIG_UEC_ETH1
388 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
389 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
390 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
391 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
392 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
393 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
394 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
395 #endif /* CONFIG_UEC_ETH1 */
397 #define CONFIG_UEC_ETH5 /* ETH5 */
398 #define CONFIG_HAS_ETH1
400 #ifdef CONFIG_UEC_ETH5
401 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
402 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
403 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
404 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
405 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
406 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
407 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
408 #endif /* CONFIG_UEC_ETH5 */
409 #endif /* CONFIG_TWR-P1025 */
414 #ifdef CONFIG_SYS_RAMBOOT
415 #ifdef CONFIG_RAMBOOT_SDCARD
416 #define CONFIG_ENV_IS_IN_MMC
417 #define CONFIG_ENV_SIZE 0x2000
418 #define CONFIG_SYS_MMC_ENV_DEV 0
420 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
421 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
422 #define CONFIG_ENV_SIZE 0x2000
425 #define CONFIG_ENV_IS_IN_FLASH
426 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
427 #define CONFIG_ENV_ADDR 0xfff80000
429 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
431 #define CONFIG_ENV_SIZE 0x2000
432 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
435 #define CONFIG_LOADS_ECHO /* echo on for serial download */
436 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
439 * Command line configuration.
441 #include <config_cmd_default.h>
443 #define CONFIG_CMD_IRQ
444 #define CONFIG_CMD_PING
445 #define CONFIG_CMD_I2C
446 #define CONFIG_CMD_MII
447 #define CONFIG_CMD_ELF
448 #define CONFIG_CMD_SETEXPR
449 #define CONFIG_CMD_REGINFO
454 #define CONFIG_HAS_FSL_DR_USB
456 #if defined(CONFIG_HAS_FSL_DR_USB)
457 #define CONFIG_USB_EHCI
459 #ifdef CONFIG_USB_EHCI
460 #define CONFIG_CMD_USB
461 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
462 #define CONFIG_USB_EHCI_FSL
463 #define CONFIG_USB_STORAGE
470 #define CONFIG_FSL_ESDHC
471 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
472 #define CONFIG_CMD_MMC
473 #define CONFIG_GENERIC_MMC
476 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
477 || defined(CONFIG_FSL_SATA)
478 #define CONFIG_CMD_EXT2
479 #define CONFIG_CMD_FAT
480 #define CONFIG_DOS_PARTITION
483 #undef CONFIG_WATCHDOG /* watchdog disabled */
486 * Miscellaneous configurable options
488 #define CONFIG_SYS_LONGHELP /* undef to save memory */
489 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
490 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
491 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
492 #if defined(CONFIG_CMD_KGDB)
493 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
495 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
497 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
498 /* Print Buffer Size */
499 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
500 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
501 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
504 * For booting Linux, the board info and command line data
505 * have to be in the first 64 MB of memory, since this is
506 * the maximum mapped by the Linux kernel during initialization.
508 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
509 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
512 * Environment Configuration
514 #define CONFIG_HOSTNAME unknown
515 #define CONFIG_ROOTPATH "/opt/nfsroot"
516 #define CONFIG_BOOTFILE "uImage"
517 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
519 /* default location for tftp and bootm */
520 #define CONFIG_LOADADDR 1000000
522 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
523 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
525 #define CONFIG_BAUDRATE 115200
527 #define CONFIG_EXTRA_ENV_SETTINGS \
529 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
530 "loadaddr=1000000\0" \
531 "bootfile=uImage\0" \
532 "dtbfile=twr-p1025twr.dtb\0" \
533 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
534 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
535 "tftpflash=tftpboot $loadaddr $uboot; " \
536 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
537 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
538 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
539 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
540 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
541 "kernelflash=tftpboot $loadaddr $bootfile; " \
542 "protect off 0xefa80000 +$filesize; " \
543 "erase 0xefa80000 +$filesize; " \
544 "cp.b $loadaddr 0xefa80000 $filesize; " \
545 "protect on 0xefa80000 +$filesize; " \
546 "cmp.b $loadaddr 0xefa80000 $filesize\0" \
547 "dtbflash=tftpboot $loadaddr $dtbfile; " \
548 "protect off 0xefe80000 +$filesize; " \
549 "erase 0xefe80000 +$filesize; " \
550 "cp.b $loadaddr 0xefe80000 $filesize; " \
551 "protect on 0xefe80000 +$filesize; " \
552 "cmp.b $loadaddr 0xefe80000 $filesize\0" \
553 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
554 "protect off 0xeeb80000 +$filesize; " \
555 "erase 0xeeb80000 +$filesize; " \
556 "cp.b $loadaddr 0xeeb80000 $filesize; " \
557 "protect on 0xeeb80000 +$filesize; " \
558 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \
559 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
560 "protect off 0xefec0000 +$filesize; " \
561 "erase 0xefec0000 +$filesize; " \
562 "cp.b $loadaddr 0xefec0000 $filesize; " \
563 "protect on 0xefec0000 +$filesize; " \
564 "cmp.b $loadaddr 0xefec0000 $filesize\0" \
565 "consoledev=ttyS0\0" \
566 "ramdiskaddr=2000000\0" \
567 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
570 "norbootaddr=ef080000\0" \
571 "norfdtaddr=ef040000\0" \
572 "ramdisk_size=120000\0" \
573 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
574 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
576 #define CONFIG_NFSBOOTCOMMAND \
577 "setenv bootargs root=/dev/nfs rw " \
578 "nfsroot=$serverip:$rootpath " \
579 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
580 "console=$consoledev,$baudrate $othbootargs;" \
581 "tftp $loadaddr $bootfile&&" \
582 "tftp $fdtaddr $fdtfile&&" \
583 "bootm $loadaddr - $fdtaddr"
585 #define CONFIG_HDBOOT \
586 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
587 "console=$consoledev,$baudrate $othbootargs;" \
589 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
590 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
591 "bootm $loadaddr - $fdtaddr"
593 #define CONFIG_USB_FAT_BOOT \
594 "setenv bootargs root=/dev/ram rw " \
595 "console=$consoledev,$baudrate $othbootargs " \
596 "ramdisk_size=$ramdisk_size;" \
598 "fatload usb 0:2 $loadaddr $bootfile;" \
599 "fatload usb 0:2 $fdtaddr $fdtfile;" \
600 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
601 "bootm $loadaddr $ramdiskaddr $fdtaddr"
603 #define CONFIG_USB_EXT2_BOOT \
604 "setenv bootargs root=/dev/ram rw " \
605 "console=$consoledev,$baudrate $othbootargs " \
606 "ramdisk_size=$ramdisk_size;" \
608 "ext2load usb 0:4 $loadaddr $bootfile;" \
609 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
610 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
611 "bootm $loadaddr $ramdiskaddr $fdtaddr"
613 #define CONFIG_NORBOOT \
614 "setenv bootargs root=/dev/mtdblock3 rw " \
615 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
616 "bootm $norbootaddr - $norfdtaddr"
618 #define CONFIG_RAMBOOTCOMMAND_TFTP \
619 "setenv bootargs root=/dev/ram rw " \
620 "console=$consoledev,$baudrate $othbootargs " \
621 "ramdisk_size=$ramdisk_size;" \
622 "tftp $ramdiskaddr $ramdiskfile;" \
623 "tftp $loadaddr $bootfile;" \
624 "tftp $fdtaddr $fdtfile;" \
625 "bootm $loadaddr $ramdiskaddr $fdtaddr"
627 #define CONFIG_RAMBOOTCOMMAND \
628 "setenv bootargs root=/dev/ram rw " \
629 "console=$consoledev,$baudrate $othbootargs " \
630 "ramdisk_size=$ramdisk_size;" \
631 "bootm 0xefa80000 0xeeb80000 0xefe80000"
633 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
635 #endif /* __CONFIG_H */