2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * QorIQ RDB boards configuration file
30 #define CONFIG_PHYS_64BIT
33 #if defined(CONFIG_P1020MBG)
34 #define CONFIG_BOARDNAME "P1020MBG-PC"
36 #define CONFIG_VSC7385_ENET
38 #define __SW_BOOT_MASK 0x03
39 #define __SW_BOOT_NOR 0xe4
40 #define __SW_BOOT_SD 0x54
43 #if defined(CONFIG_P1020UTM)
44 #define CONFIG_BOARDNAME "P1020UTM-PC"
46 #define __SW_BOOT_MASK 0x03
47 #define __SW_BOOT_NOR 0xe0
48 #define __SW_BOOT_SD 0x50
51 #if defined(CONFIG_P1020RDB)
52 #define CONFIG_BOARDNAME "P1020RDB-PC"
53 #define CONFIG_NAND_FSL_ELBC
55 #define CONFIG_SPI_FLASH
56 #define CONFIG_VSC7385_ENET
58 #define __SW_BOOT_MASK 0x03
59 #define __SW_BOOT_NOR 0x5c
60 #define __SW_BOOT_SPI 0x1c
61 #define __SW_BOOT_SD 0x9c
62 #define __SW_BOOT_NAND 0xec
63 #define __SW_BOOT_PCIE 0x6c
66 #if defined(CONFIG_P1021RDB)
67 #define CONFIG_BOARDNAME "P1021RDB-PC"
68 #define CONFIG_NAND_FSL_ELBC
71 #define CONFIG_SPI_FLASH
72 #define CONFIG_VSC7385_ENET
73 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
74 addresses in the LBC */
75 #define __SW_BOOT_MASK 0x03
76 #define __SW_BOOT_NOR 0x5c
77 #define __SW_BOOT_SPI 0x1c
78 #define __SW_BOOT_SD 0x9c
79 #define __SW_BOOT_NAND 0xec
80 #define __SW_BOOT_PCIE 0x6c
83 #if defined(CONFIG_P1024RDB)
84 #define CONFIG_BOARDNAME "P1024RDB"
85 #define CONFIG_NAND_FSL_ELBC
88 #define CONFIG_SPI_FLASH
89 #define __SW_BOOT_MASK 0xf3
90 #define __SW_BOOT_NOR 0x00
91 #define __SW_BOOT_SPI 0x08
92 #define __SW_BOOT_SD 0x04
93 #define __SW_BOOT_NAND 0x0c
96 #if defined(CONFIG_P1025RDB)
97 #define CONFIG_BOARDNAME "P1025RDB"
98 #define CONFIG_NAND_FSL_ELBC
102 #define CONFIG_SPI_FLASH
104 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
105 addresses in the LBC */
106 #define __SW_BOOT_MASK 0xf3
107 #define __SW_BOOT_NOR 0x00
108 #define __SW_BOOT_SPI 0x08
109 #define __SW_BOOT_SD 0x04
110 #define __SW_BOOT_NAND 0x0c
113 #if defined(CONFIG_P2020RDB)
114 #define CONFIG_BOARDNAME "P2020RDB-PCA"
115 #define CONFIG_NAND_FSL_ELBC
117 #define CONFIG_SPI_FLASH
118 #define CONFIG_VSC7385_ENET
119 #define __SW_BOOT_MASK 0x03
120 #define __SW_BOOT_NOR 0xc8
121 #define __SW_BOOT_SPI 0x28
122 #define __SW_BOOT_SD 0x68 /* or 0x18 */
123 #define __SW_BOOT_NAND 0xe8
124 #define __SW_BOOT_PCIE 0xa8
128 #define CONFIG_RAMBOOT_SDCARD
129 #define CONFIG_SYS_RAMBOOT
130 #define CONFIG_SYS_EXTRA_ENV_RELOC
131 #define CONFIG_SYS_TEXT_BASE 0x11000000
132 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
135 #ifdef CONFIG_SPIFLASH
136 #define CONFIG_RAMBOOT_SPIFLASH
137 #define CONFIG_SYS_RAMBOOT
138 #define CONFIG_SYS_EXTRA_ENV_RELOC
139 #define CONFIG_SYS_TEXT_BASE 0x11000000
140 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
145 #define CONFIG_SPL_INIT_MINIMAL
146 #define CONFIG_SPL_SERIAL_SUPPORT
147 #define CONFIG_SPL_NAND_SUPPORT
148 #define CONFIG_SPL_NAND_MINIMAL
149 #define CONFIG_SPL_FLUSH_IMAGE
150 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
152 #define CONFIG_SYS_TEXT_BASE 0x00201000
153 #define CONFIG_SPL_TEXT_BASE 0xfffff000
154 #define CONFIG_SPL_MAX_SIZE (4 * 1024)
155 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
156 #define CONFIG_SPL_RELOC_STACK 0x00100000
157 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
158 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
159 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
160 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
161 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
164 #ifndef CONFIG_SYS_TEXT_BASE
165 #define CONFIG_SYS_TEXT_BASE 0xeff80000
168 #ifndef CONFIG_RESET_VECTOR_ADDRESS
169 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
172 #ifndef CONFIG_SYS_MONITOR_BASE
173 #ifdef CONFIG_SPL_BUILD
174 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
176 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
180 /* High Level Configuration Options */
183 #define CONFIG_MPC85xx
187 #define CONFIG_FSL_ELBC
189 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
190 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
191 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
192 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
193 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
195 #define CONFIG_FSL_LAW
196 #define CONFIG_TSEC_ENET /* tsec ethernet support */
197 #define CONFIG_ENV_OVERWRITE
199 #define CONFIG_CMD_SATA
200 #define CONFIG_SATA_SIL
201 #define CONFIG_SYS_SATA_MAX_DEVICE 2
202 #define CONFIG_LIBATA
205 #if defined(CONFIG_P2020RDB)
206 #define CONFIG_SYS_CLK_FREQ 100000000
208 #define CONFIG_SYS_CLK_FREQ 66666666
210 #define CONFIG_DDR_CLK_FREQ 66666666
212 #define CONFIG_HWCONFIG
214 * These can be toggled for performance analysis, otherwise use default.
216 #define CONFIG_L2_CACHE
219 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
221 #define CONFIG_ENABLE_36BIT_PHYS
223 #ifdef CONFIG_PHYS_64BIT
224 #define CONFIG_ADDR_MAP 1
225 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
228 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
229 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
230 #define CONFIG_PANIC_HANG /* do not reset board on panic */
232 #define CONFIG_SYS_CCSRBAR 0xffe00000
233 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
235 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
237 #ifdef CONFIG_SPL_BUILD
238 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
242 #define CONFIG_FSL_DDR3
243 #define CONFIG_SYS_DDR_RAW_TIMING
244 #define CONFIG_DDR_SPD
245 #define CONFIG_SYS_SPD_BUS_NUM 1
246 #define SPD_EEPROM_ADDRESS 0x52
247 #undef CONFIG_FSL_DDR_INTERACTIVE
249 #ifdef CONFIG_P1020MBG
250 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
251 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
253 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
254 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
256 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
257 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
258 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
260 #define CONFIG_NUM_DDR_CONTROLLERS 1
261 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
263 /* Default settings for DDR3 */
264 #ifdef CONFIG_P2020RDB
265 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
266 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
267 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
268 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
269 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
270 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
272 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
273 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
274 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
275 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
277 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
278 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8645F607
279 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
280 #define CONFIG_SYS_DDR_RCW_1 0x00000000
281 #define CONFIG_SYS_DDR_RCW_2 0x00000000
282 #define CONFIG_SYS_DDR_CONTROL 0xC7000000 /* Type = DDR3 */
283 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
284 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
285 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
287 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
288 #define CONFIG_SYS_DDR_TIMING_0 0x00330104
289 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4644
290 #define CONFIG_SYS_DDR_TIMING_2 0x0FA88CCF
291 #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
292 #define CONFIG_SYS_DDR_MODE_1 0x00421422
293 #define CONFIG_SYS_DDR_MODE_2 0x04000000
294 #define CONFIG_SYS_DDR_INTERVAL 0x0C300100
297 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
298 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
299 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
300 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
301 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
302 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
304 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
305 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
306 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
307 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
309 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
310 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
311 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
312 #define CONFIG_SYS_DDR_RCW_1 0x00000000
313 #define CONFIG_SYS_DDR_RCW_2 0x00000000
314 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
315 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
316 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
317 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
319 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
320 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
321 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
322 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
323 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
324 #define CONFIG_SYS_DDR_MODE_1 0x40461520
325 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
326 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
329 #undef CONFIG_CLOCKS_IN_MHZ
334 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
335 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
336 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
337 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
338 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
339 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
340 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
341 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
342 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
343 * 0xffd8_0000 0xffdf_ffff L2 SRAM Up to 512K cacheable
344 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
349 * Local Bus Definitions
351 #if defined(CONFIG_P1020MBG)
352 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
353 #define CONFIG_SYS_FLASH_BASE 0xec000000
354 #elif defined(CONFIG_P1020UTM)
355 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
356 #define CONFIG_SYS_FLASH_BASE 0xee000000
358 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
359 #define CONFIG_SYS_FLASH_BASE 0xef000000
363 #ifdef CONFIG_PHYS_64BIT
364 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
366 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
369 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
372 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
374 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
375 #define CONFIG_SYS_FLASH_QUIET_TEST
376 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
378 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
380 #undef CONFIG_SYS_FLASH_CHECKSUM
381 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
382 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
384 #define CONFIG_FLASH_CFI_DRIVER
385 #define CONFIG_SYS_FLASH_CFI
386 #define CONFIG_SYS_FLASH_EMPTY_INFO
387 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
390 #ifdef CONFIG_NAND_FSL_ELBC
391 #define CONFIG_SYS_NAND_BASE 0xff800000
392 #ifdef CONFIG_PHYS_64BIT
393 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
395 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
398 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
399 #define CONFIG_SYS_MAX_NAND_DEVICE 1
400 #define CONFIG_MTD_NAND_VERIFY_WRITE
401 #define CONFIG_CMD_NAND
402 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
404 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
405 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
406 | BR_PS_8 /* Port Size = 8 bit */ \
407 | BR_MS_FCM /* MSEL = FCM */ \
409 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
416 #endif /* CONFIG_NAND_FSL_ELBC */
418 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
420 #define CONFIG_SYS_INIT_RAM_LOCK
421 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
422 #ifdef CONFIG_PHYS_64BIT
423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
425 /* The assembler doesn't like typecast */
426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
427 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
428 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
430 /* Initial L1 address */
431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
435 /* Size of used area in RAM */
436 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
438 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
439 GENERATED_GBL_DATA_SIZE)
440 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
442 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
443 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
445 #define CONFIG_SYS_CPLD_BASE 0xffa00000
446 #ifdef CONFIG_PHYS_64BIT
447 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
449 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
451 /* CPLD config size: 1Mb */
452 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
454 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
456 #define CONFIG_SYS_PMC_BASE 0xff980000
457 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
458 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
460 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
461 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
465 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
466 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
467 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
468 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
470 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
471 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
472 #ifdef CONFIG_NAND_FSL_ELBC
473 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
474 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
477 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
478 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
482 #ifdef CONFIG_VSC7385_ENET
483 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
485 #ifdef CONFIG_PHYS_64BIT
486 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
488 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
491 #define CONFIG_SYS_VSC7385_BR_PRELIM \
492 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
493 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
494 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
495 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
497 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
498 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
500 /* The size of the VSC7385 firmware image */
501 #define CONFIG_VSC7385_IMAGE_SIZE 8192
504 /* Serial Port - controlled on board with jumper J8
508 #define CONFIG_CONS_INDEX 1
509 #undef CONFIG_SERIAL_SOFTWARE_FIFO
510 #define CONFIG_SYS_NS16550
511 #define CONFIG_SYS_NS16550_SERIAL
512 #define CONFIG_SYS_NS16550_REG_SIZE 1
513 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
514 #ifdef CONFIG_SPL_BUILD
515 #define CONFIG_NS16550_MIN_FUNCTIONS
518 #define CONFIG_SYS_BAUDRATE_TABLE \
519 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
521 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
522 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
524 /* Use the HUSH parser */
525 #define CONFIG_SYS_HUSH_PARSER
528 * Pass open firmware flat tree
530 #define CONFIG_OF_LIBFDT
531 #define CONFIG_OF_BOARD_SETUP
532 #define CONFIG_OF_STDOUT_VIA_ALIAS
534 /* new uImage format support */
536 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
539 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
540 #define CONFIG_HARD_I2C /* I2C with hardware support */
541 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
542 #define CONFIG_I2C_MULTI_BUS
543 #define CONFIG_I2C_CMD_TREE
544 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C spd and slave address */
545 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
546 #define CONFIG_SYS_I2C_SLAVE 0x7F
547 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe this addr */
548 #define CONFIG_SYS_I2C_OFFSET 0x3000
549 #define CONFIG_SYS_I2C2_OFFSET 0x3100
550 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
555 #undef CONFIG_ID_EEPROM
557 #define CONFIG_RTC_PT7C4338
558 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
559 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
561 /* enable read and write access to EEPROM */
562 #define CONFIG_CMD_EEPROM
563 #define CONFIG_SYS_I2C_MULTI_EEPROMS
564 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
565 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
566 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
569 * eSPI - Enhanced SPI
571 #define CONFIG_HARD_SPI
572 #define CONFIG_FSL_ESPI
574 #if defined(CONFIG_SPI_FLASH)
575 #define CONFIG_SPI_FLASH_SPANSION
576 #define CONFIG_CMD_SF
577 #define CONFIG_SF_DEFAULT_SPEED 10000000
578 #define CONFIG_SF_DEFAULT_MODE 0
581 #if defined(CONFIG_PCI)
584 * Memory space is mapped 1-1, but I/O space must start from 0.
587 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
588 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
589 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
590 #ifdef CONFIG_PHYS_64BIT
591 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
592 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
594 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
595 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
597 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
598 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
599 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
600 #ifdef CONFIG_PHYS_64BIT
601 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
603 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
605 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
607 /* controller 1, Slot 2, tgtid 1, Base address a000 */
608 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
609 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
610 #ifdef CONFIG_PHYS_64BIT
611 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
612 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
614 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
615 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
617 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
618 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
619 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
620 #ifdef CONFIG_PHYS_64BIT
621 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
623 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
625 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
627 #define CONFIG_PCI_PNP /* do pci plug-and-play */
628 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
629 #define CONFIG_CMD_PCI
630 #define CONFIG_CMD_NET
632 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
633 #define CONFIG_DOS_PARTITION
634 #endif /* CONFIG_PCI */
636 #if defined(CONFIG_TSEC_ENET)
637 #define CONFIG_MII /* MII PHY management */
639 #define CONFIG_TSEC1_NAME "eTSEC1"
641 #define CONFIG_TSEC2_NAME "eTSEC2"
643 #define CONFIG_TSEC3_NAME "eTSEC3"
645 #define TSEC1_PHY_ADDR 2
646 #define TSEC2_PHY_ADDR 0
647 #define TSEC3_PHY_ADDR 1
649 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
650 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
651 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
653 #define TSEC1_PHYIDX 0
654 #define TSEC2_PHYIDX 0
655 #define TSEC3_PHYIDX 0
657 #define CONFIG_ETHPRIME "eTSEC1"
659 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
661 #define CONFIG_HAS_ETH0
662 #define CONFIG_HAS_ETH1
663 #define CONFIG_HAS_ETH2
664 #endif /* CONFIG_TSEC_ENET */
667 /* QE microcode/firmware address */
668 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
669 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xefec0000
670 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
671 #endif /* CONFIG_QE */
673 #ifdef CONFIG_P1025RDB
675 * QE UEC ethernet configuration
677 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
679 #undef CONFIG_UEC_ETH
680 #define CONFIG_PHY_MODE_NEED_CHANGE
682 #define CONFIG_UEC_ETH1 /* ETH1 */
683 #define CONFIG_HAS_ETH0
685 #ifdef CONFIG_UEC_ETH1
686 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
687 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
688 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
689 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
690 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
691 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
692 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
693 #endif /* CONFIG_UEC_ETH1 */
695 #define CONFIG_UEC_ETH5 /* ETH5 */
696 #define CONFIG_HAS_ETH1
698 #ifdef CONFIG_UEC_ETH5
699 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
700 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
701 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
702 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
703 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
704 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
705 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
706 #endif /* CONFIG_UEC_ETH5 */
707 #endif /* CONFIG_P1025RDB */
712 #ifdef CONFIG_RAMBOOT_SPIFLASH
713 #define CONFIG_ENV_IS_IN_SPI_FLASH
714 #define CONFIG_ENV_SPI_BUS 0
715 #define CONFIG_ENV_SPI_CS 0
716 #define CONFIG_ENV_SPI_MAX_HZ 10000000
717 #define CONFIG_ENV_SPI_MODE 0
718 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
719 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
720 #define CONFIG_ENV_SECT_SIZE 0x10000
721 #elif defined(CONFIG_RAMBOOT_SDCARD)
722 #define CONFIG_ENV_IS_IN_MMC
723 #define CONFIG_FSL_FIXED_MMC_LOCATION
724 #define CONFIG_ENV_SIZE 0x2000
725 #define CONFIG_SYS_MMC_ENV_DEV 0
726 #elif defined(CONFIG_NAND)
727 #define CONFIG_ENV_IS_IN_NAND
728 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
729 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
730 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
731 #elif defined(CONFIG_SYS_RAMBOOT)
732 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
733 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
734 #define CONFIG_ENV_SIZE 0x2000
736 #define CONFIG_ENV_IS_IN_FLASH
737 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
738 #define CONFIG_ENV_ADDR 0xfff80000
740 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
742 #define CONFIG_ENV_SIZE 0x2000
743 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
746 #define CONFIG_LOADS_ECHO /* echo on for serial download */
747 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
750 * Command line configuration.
752 #include <config_cmd_default.h>
754 #define CONFIG_CMD_IRQ
755 #define CONFIG_CMD_PING
756 #define CONFIG_CMD_I2C
757 #define CONFIG_CMD_MII
758 #define CONFIG_CMD_DATE
759 #define CONFIG_CMD_ELF
760 #define CONFIG_CMD_SETEXPR
761 #define CONFIG_CMD_REGINFO
766 #define CONFIG_HAS_FSL_DR_USB
768 #if defined(CONFIG_HAS_FSL_DR_USB)
769 #define CONFIG_USB_EHCI
771 #ifdef CONFIG_USB_EHCI
772 #define CONFIG_CMD_USB
773 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
774 #define CONFIG_USB_EHCI_FSL
775 #define CONFIG_USB_STORAGE
782 #define CONFIG_FSL_ESDHC
783 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
784 #define CONFIG_CMD_MMC
785 #define CONFIG_GENERIC_MMC
788 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
789 || defined(CONFIG_FSL_SATA)
790 #define CONFIG_CMD_EXT2
791 #define CONFIG_CMD_FAT
792 #define CONFIG_DOS_PARTITION
795 #undef CONFIG_WATCHDOG /* watchdog disabled */
798 * Miscellaneous configurable options
800 #define CONFIG_SYS_LONGHELP /* undef to save memory */
801 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
802 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
803 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
804 #if defined(CONFIG_CMD_KGDB)
805 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
807 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
809 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
810 /* Print Buffer Size */
811 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
812 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
813 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
816 * For booting Linux, the board info and command line data
817 * have to be in the first 64 MB of memory, since this is
818 * the maximum mapped by the Linux kernel during initialization.
820 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
821 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
823 #if defined(CONFIG_CMD_KGDB)
824 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
825 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
829 * Environment Configuration
831 #define CONFIG_HOSTNAME unknown
832 #define CONFIG_ROOTPATH "/opt/nfsroot"
833 #define CONFIG_BOOTFILE "uImage"
834 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
836 /* default location for tftp and bootm */
837 #define CONFIG_LOADADDR 1000000
839 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
840 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
842 #define CONFIG_BAUDRATE 115200
845 #define __NOR_RST_CMD \
846 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
847 i2c mw 18 3 __SW_BOOT_MASK 1; reset
850 #define __SPI_RST_CMD \
851 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
852 i2c mw 18 3 __SW_BOOT_MASK 1; reset
855 #define __SD_RST_CMD \
856 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
857 i2c mw 18 3 __SW_BOOT_MASK 1; reset
859 #ifdef __SW_BOOT_NAND
860 #define __NAND_RST_CMD \
861 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
862 i2c mw 18 3 __SW_BOOT_MASK 1; reset
864 #ifdef __SW_BOOT_PCIE
865 #define __PCIE_RST_CMD \
866 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
867 i2c mw 18 3 __SW_BOOT_MASK 1; reset
870 #define CONFIG_EXTRA_ENV_SETTINGS \
872 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
873 "loadaddr=1000000\0" \
874 "bootfile=uImage\0" \
875 "tftpflash=tftpboot $loadaddr $uboot; " \
876 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
877 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
878 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
879 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
880 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
881 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
882 "consoledev=ttyS0\0" \
883 "ramdiskaddr=2000000\0" \
884 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
887 "jffs2nor=mtdblock3\0" \
888 "norbootaddr=ef080000\0" \
889 "norfdtaddr=ef040000\0" \
890 "jffs2nand=mtdblock9\0" \
891 "nandbootaddr=100000\0" \
892 "nandfdtaddr=80000\0" \
893 "ramdisk_size=120000\0" \
894 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
895 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
896 __stringify(__NOR_RST_CMD)"\0" \
897 __stringify(__SPI_RST_CMD)"\0" \
898 __stringify(__SD_RST_CMD)"\0" \
899 __stringify(__NAND_RST_CMD)"\0" \
900 __stringify(__PCIE_RST_CMD)"\0"
902 #define CONFIG_NFSBOOTCOMMAND \
903 "setenv bootargs root=/dev/nfs rw " \
904 "nfsroot=$serverip:$rootpath " \
905 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
906 "console=$consoledev,$baudrate $othbootargs;" \
907 "tftp $loadaddr $bootfile;" \
908 "tftp $fdtaddr $fdtfile;" \
909 "bootm $loadaddr - $fdtaddr"
911 #define CONFIG_HDBOOT \
912 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
913 "console=$consoledev,$baudrate $othbootargs;" \
915 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
916 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
917 "bootm $loadaddr - $fdtaddr"
919 #define CONFIG_USB_FAT_BOOT \
920 "setenv bootargs root=/dev/ram rw " \
921 "console=$consoledev,$baudrate $othbootargs " \
922 "ramdisk_size=$ramdisk_size;" \
924 "fatload usb 0:2 $loadaddr $bootfile;" \
925 "fatload usb 0:2 $fdtaddr $fdtfile;" \
926 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
927 "bootm $loadaddr $ramdiskaddr $fdtaddr"
929 #define CONFIG_USB_EXT2_BOOT \
930 "setenv bootargs root=/dev/ram rw " \
931 "console=$consoledev,$baudrate $othbootargs " \
932 "ramdisk_size=$ramdisk_size;" \
934 "ext2load usb 0:4 $loadaddr $bootfile;" \
935 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
936 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
937 "bootm $loadaddr $ramdiskaddr $fdtaddr"
939 #define CONFIG_NORBOOT \
940 "setenv bootargs root=/dev/$jffs2nor rw " \
941 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
942 "bootm $norbootaddr - $norfdtaddr"
944 #define CONFIG_RAMBOOTCOMMAND \
945 "setenv bootargs root=/dev/ram rw " \
946 "console=$consoledev,$baudrate $othbootargs " \
947 "ramdisk_size=$ramdisk_size;" \
948 "tftp $ramdiskaddr $ramdiskfile;" \
949 "tftp $loadaddr $bootfile;" \
950 "tftp $fdtaddr $fdtfile;" \
951 "bootm $loadaddr $ramdiskaddr $fdtaddr"
953 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
955 #endif /* __CONFIG_H */