1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * QorIQ RDB boards configuration file
12 #if defined(CONFIG_TARGET_P1020MBG)
13 #define CONFIG_BOARDNAME "P1020MBG-PC"
14 #define CONFIG_VSC7385_ENET
16 #define __SW_BOOT_MASK 0x03
17 #define __SW_BOOT_NOR 0xe4
18 #define __SW_BOOT_SD 0x54
19 #define CONFIG_SYS_L2_SIZE (256 << 10)
22 #if defined(CONFIG_TARGET_P1020UTM)
23 #define CONFIG_BOARDNAME "P1020UTM-PC"
24 #define __SW_BOOT_MASK 0x03
25 #define __SW_BOOT_NOR 0xe0
26 #define __SW_BOOT_SD 0x50
27 #define CONFIG_SYS_L2_SIZE (256 << 10)
30 #if defined(CONFIG_TARGET_P1020RDB_PC)
31 #define CONFIG_BOARDNAME "P1020RDB-PC"
32 #define CONFIG_NAND_FSL_ELBC
33 #define CONFIG_VSC7385_ENET
35 #define __SW_BOOT_MASK 0x03
36 #define __SW_BOOT_NOR 0x5c
37 #define __SW_BOOT_SPI 0x1c
38 #define __SW_BOOT_SD 0x9c
39 #define __SW_BOOT_NAND 0xec
40 #define __SW_BOOT_PCIE 0x6c
41 #define CONFIG_SYS_L2_SIZE (256 << 10)
45 * P1020RDB-PD board has user selectable switches for evaluating different
46 * frequency and boot options for the P1020 device. The table that
47 * follow describe the available options. The front six binary number was in
48 * accordance with SW3[1:6].
49 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
50 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
51 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
52 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
53 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
54 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
55 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
57 #if defined(CONFIG_TARGET_P1020RDB_PD)
58 #define CONFIG_BOARDNAME "P1020RDB-PD"
59 #define CONFIG_NAND_FSL_ELBC
60 #define CONFIG_VSC7385_ENET
62 #define __SW_BOOT_MASK 0x03
63 #define __SW_BOOT_NOR 0x64
64 #define __SW_BOOT_SPI 0x34
65 #define __SW_BOOT_SD 0x24
66 #define __SW_BOOT_NAND 0x44
67 #define __SW_BOOT_PCIE 0x74
68 #define CONFIG_SYS_L2_SIZE (256 << 10)
70 * Dynamic MTD Partition support with mtdparts
74 #if defined(CONFIG_TARGET_P1021RDB)
75 #define CONFIG_BOARDNAME "P1021RDB-PC"
76 #define CONFIG_NAND_FSL_ELBC
77 #define CONFIG_VSC7385_ENET
78 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
79 addresses in the LBC */
80 #define __SW_BOOT_MASK 0x03
81 #define __SW_BOOT_NOR 0x5c
82 #define __SW_BOOT_SPI 0x1c
83 #define __SW_BOOT_SD 0x9c
84 #define __SW_BOOT_NAND 0xec
85 #define __SW_BOOT_PCIE 0x6c
86 #define CONFIG_SYS_L2_SIZE (256 << 10)
88 * Dynamic MTD Partition support with mtdparts
92 #if defined(CONFIG_TARGET_P1024RDB)
93 #define CONFIG_BOARDNAME "P1024RDB"
94 #define CONFIG_NAND_FSL_ELBC
96 #define __SW_BOOT_MASK 0xf3
97 #define __SW_BOOT_NOR 0x00
98 #define __SW_BOOT_SPI 0x08
99 #define __SW_BOOT_SD 0x04
100 #define __SW_BOOT_NAND 0x0c
101 #define CONFIG_SYS_L2_SIZE (256 << 10)
104 #if defined(CONFIG_TARGET_P1025RDB)
105 #define CONFIG_BOARDNAME "P1025RDB"
106 #define CONFIG_NAND_FSL_ELBC
109 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
110 addresses in the LBC */
111 #define __SW_BOOT_MASK 0xf3
112 #define __SW_BOOT_NOR 0x00
113 #define __SW_BOOT_SPI 0x08
114 #define __SW_BOOT_SD 0x04
115 #define __SW_BOOT_NAND 0x0c
116 #define CONFIG_SYS_L2_SIZE (256 << 10)
119 #if defined(CONFIG_TARGET_P2020RDB)
120 #define CONFIG_BOARDNAME "P2020RDB-PC"
121 #define CONFIG_NAND_FSL_ELBC
122 #define CONFIG_VSC7385_ENET
123 #define __SW_BOOT_MASK 0x03
124 #define __SW_BOOT_NOR 0xc8
125 #define __SW_BOOT_SPI 0x28
126 #define __SW_BOOT_SD 0x68 /* or 0x18 */
127 #define __SW_BOOT_NAND 0xe8
128 #define __SW_BOOT_PCIE 0xa8
129 #define CONFIG_SYS_L2_SIZE (512 << 10)
131 * Dynamic MTD Partition support with mtdparts
136 #define CONFIG_SPL_FLUSH_IMAGE
137 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
138 #define CONFIG_SPL_PAD_TO 0x20000
139 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
140 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
141 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
142 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
143 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
144 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
145 #ifdef CONFIG_SPL_BUILD
146 #define CONFIG_SPL_COMMON_INIT_DDR
150 #ifdef CONFIG_SPIFLASH
151 #define CONFIG_SPL_SPI_FLASH_MINIMAL
152 #define CONFIG_SPL_FLUSH_IMAGE
153 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
154 #define CONFIG_SPL_PAD_TO 0x20000
155 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
156 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
157 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
158 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
159 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
160 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
161 #ifdef CONFIG_SPL_BUILD
162 #define CONFIG_SPL_COMMON_INIT_DDR
167 #ifdef CONFIG_TPL_BUILD
168 #define CONFIG_SPL_FLUSH_IMAGE
169 #define CONFIG_SPL_NAND_INIT
170 #define CONFIG_SPL_COMMON_INIT_DDR
171 #define CONFIG_SPL_MAX_SIZE (128 << 10)
172 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
173 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
174 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
175 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
176 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
177 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
178 #elif defined(CONFIG_SPL_BUILD)
179 #define CONFIG_SPL_INIT_MINIMAL
180 #define CONFIG_SPL_FLUSH_IMAGE
181 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
182 #define CONFIG_SPL_MAX_SIZE 4096
183 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
184 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
185 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
186 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
187 #endif /* not CONFIG_TPL_BUILD */
189 #define CONFIG_SPL_PAD_TO 0x20000
190 #define CONFIG_TPL_PAD_TO 0x20000
191 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
194 #ifndef CONFIG_RESET_VECTOR_ADDRESS
195 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
198 #ifndef CONFIG_SYS_MONITOR_BASE
199 #ifdef CONFIG_TPL_BUILD
200 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
201 #elif defined(CONFIG_SPL_BUILD)
202 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
204 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
208 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
209 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
210 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
211 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
212 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
213 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
215 #define CONFIG_ENV_OVERWRITE
217 #define CONFIG_SYS_SATA_MAX_DEVICE 2
220 #if defined(CONFIG_TARGET_P2020RDB)
221 #define CONFIG_SYS_CLK_FREQ 100000000
223 #define CONFIG_SYS_CLK_FREQ 66666666
225 #define CONFIG_DDR_CLK_FREQ 66666666
227 #define CONFIG_HWCONFIG
229 * These can be toggled for performance analysis, otherwise use default.
231 #define CONFIG_L2_CACHE
234 #define CONFIG_ENABLE_36BIT_PHYS
236 #ifdef CONFIG_PHYS_64BIT
237 #define CONFIG_ADDR_MAP 1
238 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
241 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
242 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
244 #define CONFIG_SYS_CCSRBAR 0xffe00000
245 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
247 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
249 #ifdef CONFIG_SPL_BUILD
250 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
254 #define CONFIG_SYS_DDR_RAW_TIMING
255 #define CONFIG_DDR_SPD
256 #define CONFIG_SYS_SPD_BUS_NUM 1
257 #define SPD_EEPROM_ADDRESS 0x52
259 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
260 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
261 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
263 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
264 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
266 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
267 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
268 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
270 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
272 /* Default settings for DDR3 */
273 #ifndef CONFIG_TARGET_P2020RDB
274 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
275 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
276 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
277 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
278 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
279 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
281 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
282 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
283 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
284 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
286 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
287 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
288 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
289 #define CONFIG_SYS_DDR_RCW_1 0x00000000
290 #define CONFIG_SYS_DDR_RCW_2 0x00000000
291 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
292 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
293 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
294 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
296 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
297 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
298 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
299 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
300 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
301 #define CONFIG_SYS_DDR_MODE_1 0x40461520
302 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
303 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
306 #undef CONFIG_CLOCKS_IN_MHZ
311 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
312 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
313 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
314 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
316 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
317 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
318 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
319 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
320 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
321 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
322 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
326 * Local Bus Definitions
328 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
329 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
330 #define CONFIG_SYS_FLASH_BASE 0xec000000
331 #elif defined(CONFIG_TARGET_P1020UTM)
332 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
333 #define CONFIG_SYS_FLASH_BASE 0xee000000
335 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
336 #define CONFIG_SYS_FLASH_BASE 0xef000000
339 #ifdef CONFIG_PHYS_64BIT
340 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
342 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
345 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
348 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
350 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
351 #define CONFIG_SYS_FLASH_QUIET_TEST
352 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
354 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
356 #undef CONFIG_SYS_FLASH_CHECKSUM
357 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
358 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
360 #define CONFIG_SYS_FLASH_EMPTY_INFO
363 #ifdef CONFIG_NAND_FSL_ELBC
364 #define CONFIG_SYS_NAND_BASE 0xff800000
365 #ifdef CONFIG_PHYS_64BIT
366 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
368 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
371 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
372 #define CONFIG_SYS_MAX_NAND_DEVICE 1
373 #if defined(CONFIG_TARGET_P1020RDB_PD)
374 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
376 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
379 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
380 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
381 | BR_PS_8 /* Port Size = 8 bit */ \
382 | BR_MS_FCM /* MSEL = FCM */ \
384 #if defined(CONFIG_TARGET_P1020RDB_PD)
385 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
386 | OR_FCM_PGS /* Large Page*/ \
394 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
402 #endif /* CONFIG_NAND_FSL_ELBC */
404 #define CONFIG_SYS_INIT_RAM_LOCK
405 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
406 #ifdef CONFIG_PHYS_64BIT
407 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
408 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
409 /* The assembler doesn't like typecast */
410 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
411 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
412 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
414 /* Initial L1 address */
415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
416 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
417 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
419 /* Size of used area in RAM */
420 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
422 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
423 GENERATED_GBL_DATA_SIZE)
424 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
426 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
427 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
429 #define CONFIG_SYS_CPLD_BASE 0xffa00000
430 #ifdef CONFIG_PHYS_64BIT
431 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
433 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
435 /* CPLD config size: 1Mb */
436 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
438 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
440 #define CONFIG_SYS_PMC_BASE 0xff980000
441 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
442 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
444 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
445 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
449 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
450 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
451 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
452 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
454 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
455 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
456 #ifdef CONFIG_NAND_FSL_ELBC
457 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
458 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
461 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
462 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
465 #ifdef CONFIG_VSC7385_ENET
466 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
468 #ifdef CONFIG_PHYS_64BIT
469 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
471 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
474 #define CONFIG_SYS_VSC7385_BR_PRELIM \
475 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
476 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
477 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
478 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
480 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
481 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
483 /* The size of the VSC7385 firmware image */
484 #define CONFIG_VSC7385_IMAGE_SIZE 8192
488 * Config the L2 Cache as L2 SRAM
490 #if defined(CONFIG_SPL_BUILD)
491 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
492 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
493 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
494 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
495 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
496 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
497 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
498 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
499 #if defined(CONFIG_TARGET_P2020RDB)
500 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
502 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
504 #elif defined(CONFIG_NAND)
505 #ifdef CONFIG_TPL_BUILD
506 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
507 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
508 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
509 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
510 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
511 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
512 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
513 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
515 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
516 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
517 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
518 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
519 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
520 #endif /* CONFIG_TPL_BUILD */
524 /* Serial Port - controlled on board with jumper J8
528 #undef CONFIG_SERIAL_SOFTWARE_FIFO
529 #define CONFIG_SYS_NS16550_SERIAL
530 #define CONFIG_SYS_NS16550_REG_SIZE 1
531 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
532 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
533 #define CONFIG_NS16550_MIN_FUNCTIONS
536 #define CONFIG_SYS_BAUDRATE_TABLE \
537 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
539 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
540 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
543 #define CONFIG_SYS_I2C
544 #define CONFIG_SYS_I2C_FSL
545 #define CONFIG_SYS_FSL_I2C_SPEED 400000
546 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
547 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
548 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
549 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
550 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
551 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
552 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
553 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
558 #undef CONFIG_ID_EEPROM
560 #define CONFIG_RTC_PT7C4338
561 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
562 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
564 /* enable read and write access to EEPROM */
565 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
566 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
567 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
569 #if defined(CONFIG_PCI)
572 * Memory space is mapped 1-1, but I/O space must start from 0.
575 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
576 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
577 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
578 #ifdef CONFIG_PHYS_64BIT
579 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
580 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
582 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
583 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
585 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
586 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
587 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
588 #ifdef CONFIG_PHYS_64BIT
589 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
591 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
593 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
595 /* controller 1, Slot 2, tgtid 1, Base address a000 */
596 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
597 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
598 #ifdef CONFIG_PHYS_64BIT
599 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
600 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
602 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
603 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
605 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
606 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
607 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
608 #ifdef CONFIG_PHYS_64BIT
609 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
611 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
613 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
615 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
616 #endif /* CONFIG_PCI */
618 #if defined(CONFIG_TSEC_ENET)
620 #define CONFIG_TSEC1_NAME "eTSEC1"
622 #define CONFIG_TSEC2_NAME "eTSEC2"
624 #define CONFIG_TSEC3_NAME "eTSEC3"
626 #define TSEC1_PHY_ADDR 2
627 #define TSEC2_PHY_ADDR 0
628 #define TSEC3_PHY_ADDR 1
630 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
631 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
632 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
634 #define TSEC1_PHYIDX 0
635 #define TSEC2_PHYIDX 0
636 #define TSEC3_PHYIDX 0
638 #define CONFIG_ETHPRIME "eTSEC1"
640 #define CONFIG_HAS_ETH0
641 #define CONFIG_HAS_ETH1
642 #define CONFIG_HAS_ETH2
643 #endif /* CONFIG_TSEC_ENET */
646 /* QE microcode/firmware address */
647 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
648 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
649 #endif /* CONFIG_QE */
651 #ifdef CONFIG_TARGET_P1025RDB
653 * QE UEC ethernet configuration
655 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
657 #undef CONFIG_UEC_ETH
658 #define CONFIG_PHY_MODE_NEED_CHANGE
660 #define CONFIG_UEC_ETH1 /* ETH1 */
661 #define CONFIG_HAS_ETH0
663 #ifdef CONFIG_UEC_ETH1
664 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
665 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
666 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
667 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
668 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
669 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
670 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
671 #endif /* CONFIG_UEC_ETH1 */
673 #define CONFIG_UEC_ETH5 /* ETH5 */
674 #define CONFIG_HAS_ETH1
676 #ifdef CONFIG_UEC_ETH5
677 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
678 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
679 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
680 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
681 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
682 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
683 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
684 #endif /* CONFIG_UEC_ETH5 */
685 #endif /* CONFIG_TARGET_P1025RDB */
690 #ifdef CONFIG_SPIFLASH
691 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
692 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
693 #define CONFIG_ENV_SECT_SIZE 0x10000
694 #elif defined(CONFIG_SDCARD)
695 #define CONFIG_FSL_FIXED_MMC_LOCATION
696 #define CONFIG_ENV_SIZE 0x2000
697 #define CONFIG_SYS_MMC_ENV_DEV 0
698 #elif defined(CONFIG_NAND)
699 #ifdef CONFIG_TPL_BUILD
700 #define CONFIG_ENV_SIZE 0x2000
701 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
703 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
705 #define CONFIG_ENV_OFFSET (1024 * 1024)
706 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
707 #elif defined(CONFIG_SYS_RAMBOOT)
708 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
709 #define CONFIG_ENV_SIZE 0x2000
711 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
712 #define CONFIG_ENV_SIZE 0x2000
713 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
716 #define CONFIG_LOADS_ECHO /* echo on for serial download */
717 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
722 #define CONFIG_HAS_FSL_DR_USB
724 #if defined(CONFIG_HAS_FSL_DR_USB)
725 #ifdef CONFIG_USB_EHCI_HCD
726 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
727 #define CONFIG_USB_EHCI_FSL
731 #if defined(CONFIG_TARGET_P1020RDB_PD)
732 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
736 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
739 #undef CONFIG_WATCHDOG /* watchdog disabled */
742 * Miscellaneous configurable options
744 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
747 * For booting Linux, the board info and command line data
748 * have to be in the first 64 MB of memory, since this is
749 * the maximum mapped by the Linux kernel during initialization.
751 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
752 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
754 #if defined(CONFIG_CMD_KGDB)
755 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
759 * Environment Configuration
761 #define CONFIG_HOSTNAME "unknown"
762 #define CONFIG_ROOTPATH "/opt/nfsroot"
763 #define CONFIG_BOOTFILE "uImage"
764 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
766 /* default location for tftp and bootm */
767 #define CONFIG_LOADADDR 1000000
770 #define __NOR_RST_CMD \
771 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
772 i2c mw 18 3 __SW_BOOT_MASK 1; reset
775 #define __SPI_RST_CMD \
776 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
777 i2c mw 18 3 __SW_BOOT_MASK 1; reset
780 #define __SD_RST_CMD \
781 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
782 i2c mw 18 3 __SW_BOOT_MASK 1; reset
784 #ifdef __SW_BOOT_NAND
785 #define __NAND_RST_CMD \
786 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
787 i2c mw 18 3 __SW_BOOT_MASK 1; reset
789 #ifdef __SW_BOOT_PCIE
790 #define __PCIE_RST_CMD \
791 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
792 i2c mw 18 3 __SW_BOOT_MASK 1; reset
795 #define CONFIG_EXTRA_ENV_SETTINGS \
797 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
798 "loadaddr=1000000\0" \
799 "bootfile=uImage\0" \
800 "tftpflash=tftpboot $loadaddr $uboot; " \
801 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
802 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
803 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
804 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
805 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
806 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
807 "consoledev=ttyS0\0" \
808 "ramdiskaddr=2000000\0" \
809 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
810 "fdtaddr=1e00000\0" \
812 "jffs2nor=mtdblock3\0" \
813 "norbootaddr=ef080000\0" \
814 "norfdtaddr=ef040000\0" \
815 "jffs2nand=mtdblock9\0" \
816 "nandbootaddr=100000\0" \
817 "nandfdtaddr=80000\0" \
818 "ramdisk_size=120000\0" \
819 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
820 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
821 __stringify(__NOR_RST_CMD)"\0" \
822 __stringify(__SPI_RST_CMD)"\0" \
823 __stringify(__SD_RST_CMD)"\0" \
824 __stringify(__NAND_RST_CMD)"\0" \
825 __stringify(__PCIE_RST_CMD)"\0"
827 #define CONFIG_NFSBOOTCOMMAND \
828 "setenv bootargs root=/dev/nfs rw " \
829 "nfsroot=$serverip:$rootpath " \
830 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
831 "console=$consoledev,$baudrate $othbootargs;" \
832 "tftp $loadaddr $bootfile;" \
833 "tftp $fdtaddr $fdtfile;" \
834 "bootm $loadaddr - $fdtaddr"
836 #define CONFIG_HDBOOT \
837 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
838 "console=$consoledev,$baudrate $othbootargs;" \
840 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
841 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
842 "bootm $loadaddr - $fdtaddr"
844 #define CONFIG_USB_FAT_BOOT \
845 "setenv bootargs root=/dev/ram rw " \
846 "console=$consoledev,$baudrate $othbootargs " \
847 "ramdisk_size=$ramdisk_size;" \
849 "fatload usb 0:2 $loadaddr $bootfile;" \
850 "fatload usb 0:2 $fdtaddr $fdtfile;" \
851 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
852 "bootm $loadaddr $ramdiskaddr $fdtaddr"
854 #define CONFIG_USB_EXT2_BOOT \
855 "setenv bootargs root=/dev/ram rw " \
856 "console=$consoledev,$baudrate $othbootargs " \
857 "ramdisk_size=$ramdisk_size;" \
859 "ext2load usb 0:4 $loadaddr $bootfile;" \
860 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
861 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
862 "bootm $loadaddr $ramdiskaddr $fdtaddr"
864 #define CONFIG_NORBOOT \
865 "setenv bootargs root=/dev/$jffs2nor rw " \
866 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
867 "bootm $norbootaddr - $norfdtaddr"
869 #define CONFIG_RAMBOOTCOMMAND \
870 "setenv bootargs root=/dev/ram rw " \
871 "console=$consoledev,$baudrate $othbootargs " \
872 "ramdisk_size=$ramdisk_size;" \
873 "tftp $ramdiskaddr $ramdiskfile;" \
874 "tftp $loadaddr $bootfile;" \
875 "tftp $fdtaddr $fdtfile;" \
876 "bootm $loadaddr $ramdiskaddr $fdtaddr"
878 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
880 #endif /* __CONFIG_H */