1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * QorIQ RDB boards configuration file
12 #if defined(CONFIG_TARGET_P1020MBG)
13 #define CONFIG_BOARDNAME "P1020MBG-PC"
14 #define CONFIG_VSC7385_ENET
16 #define __SW_BOOT_MASK 0x03
17 #define __SW_BOOT_NOR 0xe4
18 #define __SW_BOOT_SD 0x54
19 #define CONFIG_SYS_L2_SIZE (256 << 10)
22 #if defined(CONFIG_TARGET_P1020UTM)
23 #define CONFIG_BOARDNAME "P1020UTM-PC"
24 #define __SW_BOOT_MASK 0x03
25 #define __SW_BOOT_NOR 0xe0
26 #define __SW_BOOT_SD 0x50
27 #define CONFIG_SYS_L2_SIZE (256 << 10)
30 #if defined(CONFIG_TARGET_P1020RDB_PC)
31 #define CONFIG_BOARDNAME "P1020RDB-PC"
32 #define CONFIG_NAND_FSL_ELBC
33 #define CONFIG_VSC7385_ENET
35 #define __SW_BOOT_MASK 0x03
36 #define __SW_BOOT_NOR 0x5c
37 #define __SW_BOOT_SPI 0x1c
38 #define __SW_BOOT_SD 0x9c
39 #define __SW_BOOT_NAND 0xec
40 #define __SW_BOOT_PCIE 0x6c
41 #define CONFIG_SYS_L2_SIZE (256 << 10)
45 * P1020RDB-PD board has user selectable switches for evaluating different
46 * frequency and boot options for the P1020 device. The table that
47 * follow describe the available options. The front six binary number was in
48 * accordance with SW3[1:6].
49 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
50 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
51 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
52 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
53 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
54 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
55 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
57 #if defined(CONFIG_TARGET_P1020RDB_PD)
58 #define CONFIG_BOARDNAME "P1020RDB-PD"
59 #define CONFIG_NAND_FSL_ELBC
60 #define CONFIG_VSC7385_ENET
62 #define __SW_BOOT_MASK 0x03
63 #define __SW_BOOT_NOR 0x64
64 #define __SW_BOOT_SPI 0x34
65 #define __SW_BOOT_SD 0x24
66 #define __SW_BOOT_NAND 0x44
67 #define __SW_BOOT_PCIE 0x74
68 #define CONFIG_SYS_L2_SIZE (256 << 10)
70 * Dynamic MTD Partition support with mtdparts
74 #if defined(CONFIG_TARGET_P1021RDB)
75 #define CONFIG_BOARDNAME "P1021RDB-PC"
76 #define CONFIG_NAND_FSL_ELBC
78 #define CONFIG_VSC7385_ENET
79 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
80 addresses in the LBC */
81 #define __SW_BOOT_MASK 0x03
82 #define __SW_BOOT_NOR 0x5c
83 #define __SW_BOOT_SPI 0x1c
84 #define __SW_BOOT_SD 0x9c
85 #define __SW_BOOT_NAND 0xec
86 #define __SW_BOOT_PCIE 0x6c
87 #define CONFIG_SYS_L2_SIZE (256 << 10)
89 * Dynamic MTD Partition support with mtdparts
93 #if defined(CONFIG_TARGET_P1024RDB)
94 #define CONFIG_BOARDNAME "P1024RDB"
95 #define CONFIG_NAND_FSL_ELBC
97 #define __SW_BOOT_MASK 0xf3
98 #define __SW_BOOT_NOR 0x00
99 #define __SW_BOOT_SPI 0x08
100 #define __SW_BOOT_SD 0x04
101 #define __SW_BOOT_NAND 0x0c
102 #define CONFIG_SYS_L2_SIZE (256 << 10)
105 #if defined(CONFIG_TARGET_P1025RDB)
106 #define CONFIG_BOARDNAME "P1025RDB"
107 #define CONFIG_NAND_FSL_ELBC
111 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
112 addresses in the LBC */
113 #define __SW_BOOT_MASK 0xf3
114 #define __SW_BOOT_NOR 0x00
115 #define __SW_BOOT_SPI 0x08
116 #define __SW_BOOT_SD 0x04
117 #define __SW_BOOT_NAND 0x0c
118 #define CONFIG_SYS_L2_SIZE (256 << 10)
121 #if defined(CONFIG_TARGET_P2020RDB)
122 #define CONFIG_BOARDNAME "P2020RDB-PC"
123 #define CONFIG_NAND_FSL_ELBC
124 #define CONFIG_VSC7385_ENET
125 #define __SW_BOOT_MASK 0x03
126 #define __SW_BOOT_NOR 0xc8
127 #define __SW_BOOT_SPI 0x28
128 #define __SW_BOOT_SD 0x68 /* or 0x18 */
129 #define __SW_BOOT_NAND 0xe8
130 #define __SW_BOOT_PCIE 0xa8
131 #define CONFIG_SYS_L2_SIZE (512 << 10)
133 * Dynamic MTD Partition support with mtdparts
138 #define CONFIG_SPL_FLUSH_IMAGE
139 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
140 #define CONFIG_SPL_PAD_TO 0x20000
141 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
142 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
143 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
144 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
145 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
146 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
147 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
148 #define CONFIG_SPL_MMC_BOOT
149 #ifdef CONFIG_SPL_BUILD
150 #define CONFIG_SPL_COMMON_INIT_DDR
154 #ifdef CONFIG_SPIFLASH
155 #define CONFIG_SPL_SPI_FLASH_MINIMAL
156 #define CONFIG_SPL_FLUSH_IMAGE
157 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
158 #define CONFIG_SPL_PAD_TO 0x20000
159 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
160 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
161 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
162 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
163 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
164 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
165 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
166 #define CONFIG_SPL_SPI_BOOT
167 #ifdef CONFIG_SPL_BUILD
168 #define CONFIG_SPL_COMMON_INIT_DDR
173 #ifdef CONFIG_TPL_BUILD
174 #define CONFIG_SPL_NAND_BOOT
175 #define CONFIG_SPL_FLUSH_IMAGE
176 #define CONFIG_SPL_NAND_INIT
177 #define CONFIG_SPL_COMMON_INIT_DDR
178 #define CONFIG_SPL_MAX_SIZE (128 << 10)
179 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
180 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
181 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
182 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
183 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
184 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
185 #elif defined(CONFIG_SPL_BUILD)
186 #define CONFIG_SPL_INIT_MINIMAL
187 #define CONFIG_SPL_FLUSH_IMAGE
188 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
189 #define CONFIG_SPL_MAX_SIZE 4096
190 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
191 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
192 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
193 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
194 #endif /* not CONFIG_TPL_BUILD */
196 #define CONFIG_SPL_PAD_TO 0x20000
197 #define CONFIG_TPL_PAD_TO 0x20000
198 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
199 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
202 #ifndef CONFIG_RESET_VECTOR_ADDRESS
203 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
206 #ifndef CONFIG_SYS_MONITOR_BASE
207 #ifdef CONFIG_TPL_BUILD
208 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
209 #elif defined(CONFIG_SPL_BUILD)
210 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
212 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
216 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
217 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
218 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
219 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
220 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
221 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
223 #define CONFIG_ENV_OVERWRITE
225 #define CONFIG_SYS_SATA_MAX_DEVICE 2
228 #if defined(CONFIG_TARGET_P2020RDB)
229 #define CONFIG_SYS_CLK_FREQ 100000000
231 #define CONFIG_SYS_CLK_FREQ 66666666
233 #define CONFIG_DDR_CLK_FREQ 66666666
235 #define CONFIG_HWCONFIG
237 * These can be toggled for performance analysis, otherwise use default.
239 #define CONFIG_L2_CACHE
242 #define CONFIG_ENABLE_36BIT_PHYS
244 #ifdef CONFIG_PHYS_64BIT
245 #define CONFIG_ADDR_MAP 1
246 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
249 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
250 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
252 #define CONFIG_SYS_CCSRBAR 0xffe00000
253 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
255 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
257 #ifdef CONFIG_SPL_BUILD
258 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
262 #define CONFIG_SYS_DDR_RAW_TIMING
263 #define CONFIG_DDR_SPD
264 #define CONFIG_SYS_SPD_BUS_NUM 1
265 #define SPD_EEPROM_ADDRESS 0x52
267 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
268 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
269 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
271 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
272 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
274 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
275 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
276 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
278 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
280 /* Default settings for DDR3 */
281 #ifndef CONFIG_TARGET_P2020RDB
282 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
283 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
284 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
285 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
286 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
287 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
289 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
290 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
291 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
292 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
294 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
295 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
296 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
297 #define CONFIG_SYS_DDR_RCW_1 0x00000000
298 #define CONFIG_SYS_DDR_RCW_2 0x00000000
299 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
300 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
301 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
302 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
304 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
305 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
306 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
307 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
308 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
309 #define CONFIG_SYS_DDR_MODE_1 0x40461520
310 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
311 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
314 #undef CONFIG_CLOCKS_IN_MHZ
319 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
320 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
321 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
322 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
324 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
325 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
326 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
327 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
328 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
329 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
330 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
334 * Local Bus Definitions
336 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
337 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
338 #define CONFIG_SYS_FLASH_BASE 0xec000000
339 #elif defined(CONFIG_TARGET_P1020UTM)
340 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
341 #define CONFIG_SYS_FLASH_BASE 0xee000000
343 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
344 #define CONFIG_SYS_FLASH_BASE 0xef000000
347 #ifdef CONFIG_PHYS_64BIT
348 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
350 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
353 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
356 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
358 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
359 #define CONFIG_SYS_FLASH_QUIET_TEST
360 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
362 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
364 #undef CONFIG_SYS_FLASH_CHECKSUM
365 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
366 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
368 #define CONFIG_SYS_FLASH_EMPTY_INFO
371 #ifdef CONFIG_NAND_FSL_ELBC
372 #define CONFIG_SYS_NAND_BASE 0xff800000
373 #ifdef CONFIG_PHYS_64BIT
374 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
376 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
379 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
380 #define CONFIG_SYS_MAX_NAND_DEVICE 1
381 #if defined(CONFIG_TARGET_P1020RDB_PD)
382 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
384 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
387 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
388 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
389 | BR_PS_8 /* Port Size = 8 bit */ \
390 | BR_MS_FCM /* MSEL = FCM */ \
392 #if defined(CONFIG_TARGET_P1020RDB_PD)
393 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
394 | OR_FCM_PGS /* Large Page*/ \
402 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
410 #endif /* CONFIG_NAND_FSL_ELBC */
412 #define CONFIG_SYS_INIT_RAM_LOCK
413 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
414 #ifdef CONFIG_PHYS_64BIT
415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
416 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
417 /* The assembler doesn't like typecast */
418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
419 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
420 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
422 /* Initial L1 address */
423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
427 /* Size of used area in RAM */
428 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
430 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
431 GENERATED_GBL_DATA_SIZE)
432 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
434 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
435 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
437 #define CONFIG_SYS_CPLD_BASE 0xffa00000
438 #ifdef CONFIG_PHYS_64BIT
439 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
441 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
443 /* CPLD config size: 1Mb */
444 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
446 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
448 #define CONFIG_SYS_PMC_BASE 0xff980000
449 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
450 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
452 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
453 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
457 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
458 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
459 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
460 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
462 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
463 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
464 #ifdef CONFIG_NAND_FSL_ELBC
465 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
466 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
469 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
470 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
473 #ifdef CONFIG_VSC7385_ENET
474 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
476 #ifdef CONFIG_PHYS_64BIT
477 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
479 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
482 #define CONFIG_SYS_VSC7385_BR_PRELIM \
483 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
484 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
485 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
486 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
488 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
489 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
491 /* The size of the VSC7385 firmware image */
492 #define CONFIG_VSC7385_IMAGE_SIZE 8192
496 * Config the L2 Cache as L2 SRAM
498 #if defined(CONFIG_SPL_BUILD)
499 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
500 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
501 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
502 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
503 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
504 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
505 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
506 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
507 #if defined(CONFIG_TARGET_P2020RDB)
508 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
510 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
512 #elif defined(CONFIG_NAND)
513 #ifdef CONFIG_TPL_BUILD
514 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
515 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
516 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
517 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
518 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
519 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
520 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
521 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
523 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
524 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
525 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
526 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
527 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
528 #endif /* CONFIG_TPL_BUILD */
532 /* Serial Port - controlled on board with jumper J8
536 #undef CONFIG_SERIAL_SOFTWARE_FIFO
537 #define CONFIG_SYS_NS16550_SERIAL
538 #define CONFIG_SYS_NS16550_REG_SIZE 1
539 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
540 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
541 #define CONFIG_NS16550_MIN_FUNCTIONS
544 #define CONFIG_SYS_BAUDRATE_TABLE \
545 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
547 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
548 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
551 #define CONFIG_SYS_I2C
552 #define CONFIG_SYS_I2C_FSL
553 #define CONFIG_SYS_FSL_I2C_SPEED 400000
554 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
555 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
556 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
557 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
558 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
559 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
560 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
561 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
566 #undef CONFIG_ID_EEPROM
568 #define CONFIG_RTC_PT7C4338
569 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
570 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
572 /* enable read and write access to EEPROM */
573 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
574 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
575 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
577 #if defined(CONFIG_PCI)
580 * Memory space is mapped 1-1, but I/O space must start from 0.
583 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
584 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
585 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
586 #ifdef CONFIG_PHYS_64BIT
587 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
588 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
590 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
591 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
593 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
594 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
595 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
596 #ifdef CONFIG_PHYS_64BIT
597 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
599 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
601 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
603 /* controller 1, Slot 2, tgtid 1, Base address a000 */
604 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
605 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
606 #ifdef CONFIG_PHYS_64BIT
607 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
608 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
610 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
611 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
613 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
614 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
615 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
616 #ifdef CONFIG_PHYS_64BIT
617 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
619 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
621 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
623 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
624 #endif /* CONFIG_PCI */
626 #if defined(CONFIG_TSEC_ENET)
628 #define CONFIG_TSEC1_NAME "eTSEC1"
630 #define CONFIG_TSEC2_NAME "eTSEC2"
632 #define CONFIG_TSEC3_NAME "eTSEC3"
634 #define TSEC1_PHY_ADDR 2
635 #define TSEC2_PHY_ADDR 0
636 #define TSEC3_PHY_ADDR 1
638 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
639 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
640 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
642 #define TSEC1_PHYIDX 0
643 #define TSEC2_PHYIDX 0
644 #define TSEC3_PHYIDX 0
646 #define CONFIG_ETHPRIME "eTSEC1"
648 #define CONFIG_HAS_ETH0
649 #define CONFIG_HAS_ETH1
650 #define CONFIG_HAS_ETH2
651 #endif /* CONFIG_TSEC_ENET */
654 /* QE microcode/firmware address */
655 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
656 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
657 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
658 #endif /* CONFIG_QE */
660 #ifdef CONFIG_TARGET_P1025RDB
662 * QE UEC ethernet configuration
664 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
666 #undef CONFIG_UEC_ETH
667 #define CONFIG_PHY_MODE_NEED_CHANGE
669 #define CONFIG_UEC_ETH1 /* ETH1 */
670 #define CONFIG_HAS_ETH0
672 #ifdef CONFIG_UEC_ETH1
673 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
674 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
675 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
676 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
677 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
678 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
679 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
680 #endif /* CONFIG_UEC_ETH1 */
682 #define CONFIG_UEC_ETH5 /* ETH5 */
683 #define CONFIG_HAS_ETH1
685 #ifdef CONFIG_UEC_ETH5
686 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
687 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
688 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
689 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
690 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
691 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
692 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
693 #endif /* CONFIG_UEC_ETH5 */
694 #endif /* CONFIG_TARGET_P1025RDB */
699 #ifdef CONFIG_SPIFLASH
700 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
701 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
702 #define CONFIG_ENV_SECT_SIZE 0x10000
703 #elif defined(CONFIG_SDCARD)
704 #define CONFIG_FSL_FIXED_MMC_LOCATION
705 #define CONFIG_ENV_SIZE 0x2000
706 #define CONFIG_SYS_MMC_ENV_DEV 0
707 #elif defined(CONFIG_NAND)
708 #ifdef CONFIG_TPL_BUILD
709 #define CONFIG_ENV_SIZE 0x2000
710 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
712 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
714 #define CONFIG_ENV_OFFSET (1024 * 1024)
715 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
716 #elif defined(CONFIG_SYS_RAMBOOT)
717 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
718 #define CONFIG_ENV_SIZE 0x2000
720 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
721 #define CONFIG_ENV_SIZE 0x2000
722 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
725 #define CONFIG_LOADS_ECHO /* echo on for serial download */
726 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
731 #define CONFIG_HAS_FSL_DR_USB
733 #if defined(CONFIG_HAS_FSL_DR_USB)
734 #ifdef CONFIG_USB_EHCI_HCD
735 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
736 #define CONFIG_USB_EHCI_FSL
740 #if defined(CONFIG_TARGET_P1020RDB_PD)
741 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
745 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
748 #undef CONFIG_WATCHDOG /* watchdog disabled */
751 * Miscellaneous configurable options
753 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
756 * For booting Linux, the board info and command line data
757 * have to be in the first 64 MB of memory, since this is
758 * the maximum mapped by the Linux kernel during initialization.
760 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
761 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
763 #if defined(CONFIG_CMD_KGDB)
764 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
768 * Environment Configuration
770 #define CONFIG_HOSTNAME "unknown"
771 #define CONFIG_ROOTPATH "/opt/nfsroot"
772 #define CONFIG_BOOTFILE "uImage"
773 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
775 /* default location for tftp and bootm */
776 #define CONFIG_LOADADDR 1000000
779 #define __NOR_RST_CMD \
780 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
781 i2c mw 18 3 __SW_BOOT_MASK 1; reset
784 #define __SPI_RST_CMD \
785 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
786 i2c mw 18 3 __SW_BOOT_MASK 1; reset
789 #define __SD_RST_CMD \
790 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
791 i2c mw 18 3 __SW_BOOT_MASK 1; reset
793 #ifdef __SW_BOOT_NAND
794 #define __NAND_RST_CMD \
795 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
796 i2c mw 18 3 __SW_BOOT_MASK 1; reset
798 #ifdef __SW_BOOT_PCIE
799 #define __PCIE_RST_CMD \
800 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
801 i2c mw 18 3 __SW_BOOT_MASK 1; reset
804 #define CONFIG_EXTRA_ENV_SETTINGS \
806 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
807 "loadaddr=1000000\0" \
808 "bootfile=uImage\0" \
809 "tftpflash=tftpboot $loadaddr $uboot; " \
810 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
811 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
812 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
813 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
814 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
815 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
816 "consoledev=ttyS0\0" \
817 "ramdiskaddr=2000000\0" \
818 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
819 "fdtaddr=1e00000\0" \
821 "jffs2nor=mtdblock3\0" \
822 "norbootaddr=ef080000\0" \
823 "norfdtaddr=ef040000\0" \
824 "jffs2nand=mtdblock9\0" \
825 "nandbootaddr=100000\0" \
826 "nandfdtaddr=80000\0" \
827 "ramdisk_size=120000\0" \
828 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
829 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
830 __stringify(__NOR_RST_CMD)"\0" \
831 __stringify(__SPI_RST_CMD)"\0" \
832 __stringify(__SD_RST_CMD)"\0" \
833 __stringify(__NAND_RST_CMD)"\0" \
834 __stringify(__PCIE_RST_CMD)"\0"
836 #define CONFIG_NFSBOOTCOMMAND \
837 "setenv bootargs root=/dev/nfs rw " \
838 "nfsroot=$serverip:$rootpath " \
839 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
840 "console=$consoledev,$baudrate $othbootargs;" \
841 "tftp $loadaddr $bootfile;" \
842 "tftp $fdtaddr $fdtfile;" \
843 "bootm $loadaddr - $fdtaddr"
845 #define CONFIG_HDBOOT \
846 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
847 "console=$consoledev,$baudrate $othbootargs;" \
849 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
850 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
851 "bootm $loadaddr - $fdtaddr"
853 #define CONFIG_USB_FAT_BOOT \
854 "setenv bootargs root=/dev/ram rw " \
855 "console=$consoledev,$baudrate $othbootargs " \
856 "ramdisk_size=$ramdisk_size;" \
858 "fatload usb 0:2 $loadaddr $bootfile;" \
859 "fatload usb 0:2 $fdtaddr $fdtfile;" \
860 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
861 "bootm $loadaddr $ramdiskaddr $fdtaddr"
863 #define CONFIG_USB_EXT2_BOOT \
864 "setenv bootargs root=/dev/ram rw " \
865 "console=$consoledev,$baudrate $othbootargs " \
866 "ramdisk_size=$ramdisk_size;" \
868 "ext2load usb 0:4 $loadaddr $bootfile;" \
869 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
870 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
871 "bootm $loadaddr $ramdiskaddr $fdtaddr"
873 #define CONFIG_NORBOOT \
874 "setenv bootargs root=/dev/$jffs2nor rw " \
875 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
876 "bootm $norbootaddr - $norfdtaddr"
878 #define CONFIG_RAMBOOTCOMMAND \
879 "setenv bootargs root=/dev/ram rw " \
880 "console=$consoledev,$baudrate $othbootargs " \
881 "ramdisk_size=$ramdisk_size;" \
882 "tftp $ramdiskaddr $ramdiskfile;" \
883 "tftp $loadaddr $bootfile;" \
884 "tftp $fdtaddr $fdtfile;" \
885 "bootm $loadaddr $ramdiskaddr $fdtaddr"
887 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
889 #endif /* __CONFIG_H */