1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Based on davinci_dvevm.h. Original Copyrights follow:
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
16 #define CONFIG_DRIVER_TI_EMAC
17 #undef CONFIG_USE_SPIFLASH
18 #undef CONFIG_SYS_USE_NOR
21 * Disable DM_* for SPL build and can be re-enabled after adding
24 #ifdef CONFIG_SPL_BUILD
26 #undef CONFIG_DM_I2C_COMPAT
31 #define CONFIG_MACH_OMAPL138_LCDK
32 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
33 #define CONFIG_SYS_OSCIN_FREQ 24000000
34 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
35 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
36 #define CONFIG_SYS_HZ 1000
37 #define CONFIG_SKIP_LOWLEVEL_INIT
42 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
43 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
44 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
45 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
47 /* memtest start addr */
48 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
50 /* memtest will be run on 16MB */
51 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
53 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
54 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
55 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
56 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
57 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
58 DAVINCI_SYSCFG_SUSPSRC_I2C)
64 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
65 #define CONFIG_SYS_DA850_PLL0_PLLM 18
66 #define CONFIG_SYS_DA850_PLL1_PLLM 21
69 * DDR2 memory configuration
71 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
72 DV_DDR_PHY_EXT_STRBEN | \
73 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
75 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
76 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
77 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
78 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
79 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
80 (4 << DV_DDR_SDCR_CL_SHIFT) | \
81 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
82 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
84 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
85 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
87 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
88 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
89 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
90 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
91 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
92 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
93 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
94 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
95 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
97 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
98 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
99 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
100 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
101 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
102 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
103 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
104 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
106 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
107 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
112 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
113 #if !defined(CONFIG_DM_SERIAL)
114 #define CONFIG_SYS_NS16550_SERIAL
115 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
116 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
117 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
118 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
121 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
122 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
123 #define CONFIG_SF_DEFAULT_SPEED 30000000
124 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
126 #ifdef CONFIG_USE_SPIFLASH
127 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
128 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
134 #define CONFIG_SYS_I2C_DAVINCI
135 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
136 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
137 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
140 * Flash & Environment
143 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
144 #define CONFIG_ENV_SIZE (128 << 9)
145 #define CONFIG_SYS_NAND_USE_FLASH_BBT
146 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
147 #define CONFIG_SYS_NAND_PAGE_2K
148 #define CONFIG_SYS_NAND_CS 3
149 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
150 #define CONFIG_SYS_NAND_MASK_CLE 0x10
151 #define CONFIG_SYS_NAND_MASK_ALE 0x8
152 #undef CONFIG_SYS_NAND_HW_ECC
153 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
154 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
155 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
156 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
157 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
158 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
159 #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
160 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
161 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
162 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
163 CONFIG_SYS_NAND_U_BOOT_SIZE - \
164 CONFIG_SYS_MALLOC_LEN - \
165 GENERATED_GBL_DATA_SIZE)
166 #define CONFIG_SYS_NAND_ECCPOS { \
167 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
168 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
169 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
170 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
171 #define CONFIG_SYS_NAND_PAGE_COUNT 64
172 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
173 #define CONFIG_SYS_NAND_ECCSIZE 512
174 #define CONFIG_SYS_NAND_ECCBYTES 10
175 #define CONFIG_SYS_NAND_OOBSIZE 64
176 #define CONFIG_SPL_NAND_BASE
177 #define CONFIG_SPL_NAND_DRIVERS
178 #define CONFIG_SPL_NAND_ECC
179 #define CONFIG_SPL_NAND_LOAD
182 #ifdef CONFIG_SYS_USE_NOR
183 #define CONFIG_FLASH_CFI_DRIVER
184 #define CONFIG_SYS_FLASH_CFI
185 #define CONFIG_SYS_FLASH_PROTECTION
186 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
187 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
188 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
189 #define CONFIG_ENV_SIZE (128 << 10)
190 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
191 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
192 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
194 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
197 #ifdef CONFIG_USE_SPIFLASH
198 #define CONFIG_ENV_SIZE (64 << 10)
199 #define CONFIG_ENV_OFFSET (256 << 10)
200 #define CONFIG_ENV_SECT_SIZE (64 << 10)
204 * Network & Ethernet Configuration
206 #ifdef CONFIG_DRIVER_TI_EMAC
208 #undef CONFIG_DRIVER_TI_EMAC_USE_RMII
209 #define CONFIG_BOOTP_DEFAULT
210 #define CONFIG_BOOTP_DNS2
211 #define CONFIG_BOOTP_SEND_HOSTNAME
212 #define CONFIG_NET_RETRY_COUNT 10
216 * U-Boot general configuration
218 #define CONFIG_MISC_INIT_R
219 #define CONFIG_BOOTFILE "zImage" /* Boot file name */
220 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
221 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
222 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
223 #define CONFIG_MX_CYCLIC
228 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
229 #define CONFIG_CMDLINE_TAG
230 #define CONFIG_REVISION_TAG
231 #define CONFIG_SETUP_MEMORY_TAGS
232 #define CONFIG_BOOTCOMMAND \
236 #define DEFAULT_LINUX_BOOT_ENV \
237 "loadaddr=0xc0700000\0" \
238 "fdtaddr=0xc0600000\0" \
239 "scriptaddr=0xc0600000\0"
241 #include <environment/ti/mmc.h>
243 #define CONFIG_EXTRA_ENV_SETTINGS \
244 DEFAULT_LINUX_BOOT_ENV \
245 DEFAULT_MMC_TI_ARGS \
248 "bootfile=zImage\0" \
249 "fdtfile=da850-lcdk.dtb\0" \
252 "console=ttyS2,115200n8\0"
254 #ifdef CONFIG_CMD_BDI
255 #define CONFIG_CLOCKS
258 #if !defined(CONFIG_NAND) && \
259 !defined(CONFIG_SYS_USE_NOR) && \
260 !defined(CONFIG_USE_SPIFLASH)
261 #define CONFIG_ENV_SIZE (16 << 10)
266 #ifdef CONFIG_ENV_IS_IN_MMC
267 #undef CONFIG_ENV_SIZE
268 #undef CONFIG_ENV_OFFSET
269 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
270 #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
273 #ifndef CONFIG_DIRECT_NOR_BOOT
274 /* defines for SPL */
275 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
276 CONFIG_SYS_MALLOC_LEN)
277 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
278 #define CONFIG_SPL_STACK 0x8001ff00
279 #define CONFIG_SPL_TEXT_BASE 0x80000000
280 #define CONFIG_SPL_MAX_FOOTPRINT 32768
281 #define CONFIG_SPL_PAD_TO 32768
284 /* additions for new relocation code, must added to all boards */
285 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
286 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
287 GENERATED_GBL_DATA_SIZE)
289 #include <asm/arch/hardware.h>
291 #endif /* __CONFIG_H */