2 * (C) Copyright 2006-2009
3 * Texas Instruments Incorporated.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * Nishanth Menon <nm@ti.com>
8 * Configuration settings for the 3430 TI SDP3430 board.
10 * SPDX-License-Identifier: GPL-2.0+
16 /* TODO: REMOVE THE FOLLOWING
17 * Retained the following till size.h is removed in u-boot
19 #include <linux/sizes.h>
21 * High Level Configuration Options
23 #define CONFIG_OMAP 1 /* in a TI OMAP core */
24 #define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
25 #define CONFIG_OMAP_COMMON
26 /* Common ARM Erratas */
27 #define CONFIG_ARM_ERRATA_454179
28 #define CONFIG_ARM_ERRATA_430973
29 #define CONFIG_ARM_ERRATA_621766
31 #define CONFIG_SDRC /* The chip has SDRC controller */
33 #include <asm/arch/cpu.h> /* get chip and board defs */
34 #include <asm/arch/omap.h>
37 * NOTE: these #defines presume standard SDP jumper settings.
39 * - 26 MHz clock (not 19.2 or 38.4 MHz)
40 * - Boot from 128MB NOR, not NAND or OneNAND
42 * At this writing, OMAP3 U-Boot support doesn't permit concurrent
43 * support for all the flash types the board supports.
45 #define CONFIG_DISPLAY_CPUINFO 1
46 #define CONFIG_DISPLAY_BOARDINFO 1
49 #define V_OSCK 26000000 /* Clock output from T2 */
50 #define V_SCLK (V_OSCK >> 1)
52 #define CONFIG_MISC_INIT_R
54 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
55 #define CONFIG_SETUP_MEMORY_TAGS 1
56 #define CONFIG_INITRD_TAG 1
57 #define CONFIG_REVISION_TAG 1
59 #define CONFIG_OF_LIBFDT 1
62 * Size of malloc() pool
63 * Total Size Environment - 256k
66 #define CONFIG_ENV_SIZE (256 << 10)
67 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
69 /*--------------------------------------------------------------------------*/
78 #define CONFIG_TWL4030_POWER 1
81 * serial port - NS16550 compatible
83 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
85 #define CONFIG_SYS_NS16550
86 #define CONFIG_SYS_NS16550_SERIAL
87 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
88 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
90 /* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
91 * swapped with UART2 via jumpering. Downsides of using J8: it doesn't
92 * support UART boot (that's only for UART3); it prevents sharing a Linux
93 * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
95 * UART boot uses UART3 on J9, and the SDP user's guide says to use
96 * that for console. Downsides of using J9: you can't use IRDA too;
97 * since UART3 isn't in the CORE power domain, it may be a bit less
98 * usable in certain PM-sensitive debug scenarios.
100 #undef CONSOLE_J9 /* else J8/UART1 (innermost) */
103 #define CONFIG_CONS_INDEX 3
104 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
105 #define CONFIG_SERIAL3 3 /* UART3 */
107 #define CONFIG_CONS_INDEX 1
108 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
109 #define CONFIG_SERIAL1 1 /* UART1 */
112 #define CONFIG_ENV_OVERWRITE
113 #define CONFIG_BAUDRATE 115200
114 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
118 * I2C for power management setup
120 #define CONFIG_SYS_I2C
121 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
122 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
123 #define CONFIG_SYS_I2C_OMAP34XX
125 /* OMITTED: single 1 Gbit MT29F1G NAND flash */
128 * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
130 #define CONFIG_SYS_FLASH_BASE 0x10000000
131 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
132 #define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
133 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
134 #define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
135 #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
136 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
137 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
139 #define CONFIG_SYS_FLASH_CFI_WIDTH 2
140 #define PHYS_FLASH_SIZE (128 << 20)
141 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
143 /* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
145 #define CONFIG_ENV_IS_IN_FLASH 1
146 #define CONFIG_SYS_ENV_SECT_SIZE (256 << 10)
147 #define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
148 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
149 /*--------------------------------------------------------------------------*/
151 /* commands to include */
152 #include <config_cmd_default.h>
154 /* Enabled commands */
155 #define CONFIG_CMD_DHCP /* DHCP Support */
156 #define CONFIG_CMD_EXT2 /* EXT2 Support */
157 #define CONFIG_CMD_FAT /* FAT support */
158 #define CONFIG_CMD_I2C /* I2C serial bus support */
159 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
160 #define CONFIG_CMD_MMC /* MMC support */
161 #define CONFIG_CMD_NET
163 /* Disabled commands */
164 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
165 #undef CONFIG_CMD_IMLS /* List all found images */
167 /*--------------------------------------------------------------------------*/
172 #if defined(CONFIG_CMD_MMC)
173 #define CONFIG_GENERIC_MMC 1
175 #define CONFIG_OMAP_HSMMC 1
176 #define CONFIG_DOS_PARTITION 1
179 /*----------------------------------------------------------------------------
180 * SMSC9115 Ethernet from SMSC9118 family
181 *----------------------------------------------------------------------------
183 #if defined(CONFIG_CMD_NET)
185 #define CONFIG_LAN91C96
186 #define CONFIG_LAN91C96_BASE DEBUG_BASE
187 #define CONFIG_LAN91C96_EXT_PHY
189 #define CONFIG_BOOTP_SEND_HOSTNAME
193 #define CONFIG_BOOTP_SUBNETMASK 0x00000001
194 #define CONFIG_BOOTP_GATEWAY 0x00000002
195 #define CONFIG_BOOTP_HOSTNAME 0x00000004
196 #define CONFIG_BOOTP_BOOTPATH 0x00000010
197 #endif /* (CONFIG_CMD_NET) */
202 * Default boot order: mmc bootscript, MMC uImage, NOR image.
203 * Network booting environment must be configured at site.
206 /* allow overwriting serial config and ethaddr */
207 #define CONFIG_ENV_OVERWRITE
209 #define CONFIG_EXTRA_ENV_SETTINGS \
210 "loadaddr=0x82000000\0" \
211 "console=ttyS0,115200n8\0" \
212 "mmcargs=setenv bootargs console=${console} " \
213 "root=/dev/mmcblk0p2 rw " \
214 "rootfstype=ext3 rootwait\0" \
215 "norargs=setenv bootargs console=${console} " \
216 "root=/dev/mtdblock3 rw " \
217 "rootfstype=jffs2\0" \
218 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
219 "bootscript=echo Running bootscript from MMC/SD ...; " \
220 "autoscr ${loadaddr}\0" \
221 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
222 "mmcboot=echo Booting from MMC/SD ...; " \
224 "bootm ${loadaddr}\0" \
225 "norboot=echo Booting from NOR ...; " \
229 #define CONFIG_BOOTCOMMAND \
230 "if mmcinit; then " \
231 "if run loadbootscript; then " \
234 "if run loaduimage; then " \
236 "else run norboot; " \
239 "else run norboot; fi"
241 #define CONFIG_AUTO_COMPLETE 1
243 /*--------------------------------------------------------------------------*/
246 * Miscellaneous configurable options
249 #define CONFIG_SYS_LONGHELP /* undef to save memory */
250 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
251 #define CONFIG_SYS_PROMPT "OMAP34XX SDP # "
252 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
253 /* Print Buffer Size */
254 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
255 sizeof(CONFIG_SYS_PROMPT) + 16)
256 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
257 /* Boot Argument Buffer Size */
258 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
260 /* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
261 * a basic sanity check ONLY
262 * IF you would like to increase coverage, increase the end address
263 * or run the test with custom options
265 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
266 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20))
268 /* Default load address */
269 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
271 /*--------------------------------------------------------------------------*/
274 * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
275 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
277 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
278 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
280 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
281 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
282 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
283 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
284 CONFIG_SYS_INIT_RAM_SIZE - \
285 GENERATED_GBL_DATA_SIZE)
289 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
290 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
291 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
293 /*--------------------------------------------------------------------------*/
296 * NOR FLASH usage ... default nCS0:
297 * - one 256KB sector for U-Boot
298 * - one 256KB sector for its parameters (not all used)
299 * - eight sectors (2 MB) for kernel
303 /* Monitor at start of flash */
304 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
305 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
308 * NAND FLASH usage ... default nCS1:
309 * - four 128KB sectors for X-Loader
310 * - four 128KB sectors for U-Boot
311 * - two 128KB sector for its parameters
312 * - 32 sectors (4 MB) for kernel
313 * - rest for filesystem
317 * OneNAND FLASH usage ... default nCS2:
318 * - four 128KB sectors for X-Loader
319 * - two 128KB sectors for U-Boot
320 * - one 128KB sector for its parameters
321 * - sixteen sectors (2 MB) for kernel
322 * - rest for filesystem
325 #define CONFIG_SYS_CACHELINE_SIZE 64
327 #endif /* __CONFIG_H */