2 * (C) Copyright 2006-2008
5 * Manikandan Pillai <mani.pillai@ti.com>
6 * Derived from Beagle Board and 3430 SDP code by
7 * Richard Woodruff <r-woodruff2@ti.com>
8 * Syed Mohammed Khasim <khasim@ti.com>
10 * Manikandan Pillai <mani.pillai@ti.com>
12 * Configuration settings for the TI OMAP3 EVM board.
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/sizes.h>
38 * High Level Configuration Options
40 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
41 #define CONFIG_OMAP 1 /* in a TI OMAP core */
42 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
43 #define CONFIG_OMAP3430 1 /* which is in a 3430 */
44 #define CONFIG_OMAP3_EVM 1 /* working with EVM */
46 #include <asm/arch/cpu.h> /* get chip and board defs */
47 #include <asm/arch/omap3.h>
50 * Display CPU and Board information
52 #define CONFIG_DISPLAY_CPUINFO 1
53 #define CONFIG_DISPLAY_BOARDINFO 1
56 #define V_OSCK 26000000 /* Clock output from T2 */
57 #define V_SCLK (V_OSCK >> 1)
59 #undef CONFIG_USE_IRQ /* no support for IRQs */
60 #define CONFIG_MISC_INIT_R
62 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
63 #define CONFIG_SETUP_MEMORY_TAGS 1
64 #define CONFIG_INITRD_TAG 1
65 #define CONFIG_REVISION_TAG 1
68 * Size of malloc() pool
70 #define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
72 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
73 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
80 * NS16550 Configuration
82 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
84 #define CONFIG_SYS_NS16550
85 #define CONFIG_SYS_NS16550_SERIAL
86 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
87 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
90 * select serial console configuration
92 #define CONFIG_CONS_INDEX 1
93 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
94 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
96 /* allow to overwrite serial and ethaddr */
97 #define CONFIG_ENV_OVERWRITE
98 #define CONFIG_BAUDRATE 115200
99 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
102 #define CONFIG_OMAP3_MMC 1
103 #define CONFIG_DOS_PARTITION 1
105 /* commands to include */
106 #include <config_cmd_default.h>
108 #define CONFIG_CMD_EXT2 /* EXT2 Support */
109 #define CONFIG_CMD_FAT /* FAT support */
110 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
112 #define CONFIG_CMD_I2C /* I2C serial bus support */
113 #define CONFIG_CMD_MMC /* MMC support */
114 #define CONFIG_CMD_ONENAND /* ONENAND support */
115 #define CONFIG_CMD_DHCP
116 #define CONFIG_CMD_PING
118 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
119 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
120 #undef CONFIG_CMD_IMI /* iminfo */
121 #undef CONFIG_CMD_IMLS /* List all found images */
123 #define CONFIG_SYS_NO_FLASH
124 #define CONFIG_SYS_I2C_SPEED 100000
125 #define CONFIG_SYS_I2C_SLAVE 1
126 #define CONFIG_SYS_I2C_BUS 0
127 #define CONFIG_SYS_I2C_BUS_SELECT 1
128 #define CONFIG_DRIVER_OMAP34XX_I2C 1
133 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
135 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
139 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
142 #define CONFIG_JFFS2_NAND
143 /* nand device jffs2 lives on */
144 #define CONFIG_JFFS2_DEV "nand0"
145 /* start of jffs2 partition */
146 #define CONFIG_JFFS2_PART_OFFSET 0x680000
147 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
149 /* Environment information */
150 #define CONFIG_BOOTDELAY 10
152 #define CONFIG_EXTRA_ENV_SETTINGS \
153 "loadaddr=0x82000000\0" \
154 "console=ttyS2,115200n8\0" \
155 "mmcargs=setenv bootargs console=${console} " \
156 "root=/dev/mmcblk0p2 rw " \
157 "rootfstype=ext3 rootwait\0" \
158 "nandargs=setenv bootargs console=${console} " \
159 "root=/dev/mtdblock4 rw " \
160 "rootfstype=jffs2\0" \
161 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
162 "bootscript=echo Running bootscript from mmc ...; " \
163 "source ${loadaddr}\0" \
164 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
165 "mmcboot=echo Booting from mmc ...; " \
167 "bootm ${loadaddr}\0" \
168 "nandboot=echo Booting from nand ...; " \
170 "onenand read ${loadaddr} 280000 400000; " \
171 "bootm ${loadaddr}\0" \
173 #define CONFIG_BOOTCOMMAND \
174 "if mmc init; then " \
175 "if run loadbootscript; then " \
178 "if run loaduimage; then " \
180 "else run nandboot; " \
183 "else run nandboot; fi"
185 #define CONFIG_AUTO_COMPLETE 1
187 * Miscellaneous configurable options
189 #define V_PROMPT "OMAP3_EVM # "
191 #define CONFIG_SYS_LONGHELP /* undef to save memory */
192 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
193 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
194 #define CONFIG_SYS_PROMPT V_PROMPT
195 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
196 /* Print Buffer Size */
197 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
198 sizeof(CONFIG_SYS_PROMPT) + 16)
199 #define CONFIG_SYS_MAXARGS 16 /* max number of command */
201 /* Boot Argument Buffer Size */
202 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
203 /* memtest works on */
204 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
205 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
206 0x01F00000) /* 31MB */
208 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
212 * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
213 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
215 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
216 #define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
217 #define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
219 /*-----------------------------------------------------------------------
222 * The stack sizes are set up in start.S using the settings below
224 #define CONFIG_STACKSIZE SZ_128K /* regular stack */
225 #ifdef CONFIG_USE_IRQ
226 #define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
227 #define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
230 /*-----------------------------------------------------------------------
231 * Physical Memory Map
233 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
234 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
235 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
236 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
238 /* SDRAM Bank Allocation method */
241 /*-----------------------------------------------------------------------
242 * FLASH and environment organization
245 /* **** PISMO SUPPORT *** */
247 /* Configure the PISMO */
248 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
249 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
251 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
253 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
254 #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
256 #define CONFIG_SYS_FLASH_BASE boot_flash_base
258 /* Monitor at start of flash */
259 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
260 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
262 #define CONFIG_ENV_IS_IN_ONENAND 1
263 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
264 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
266 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
267 #define CONFIG_ENV_OFFSET boot_flash_off
268 #define CONFIG_ENV_ADDR boot_flash_env_addr
270 /*-----------------------------------------------------------------------
271 * CFI FLASH driver setup
273 /* timeout values are in ticks */
274 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
275 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
277 /* Flash banks JFFS2 should use */
278 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
279 CONFIG_SYS_MAX_NAND_DEVICE)
280 #define CONFIG_SYS_JFFS2_MEM_NAND
281 /* use flash_info[2] */
282 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
283 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
286 extern gpmc_csx_t *nand_cs_base;
287 extern gpmc_t *gpmc_cfg_base;
288 extern unsigned int boot_flash_base;
289 extern volatile unsigned int boot_flash_env_addr;
290 extern unsigned int boot_flash_off;
291 extern unsigned int boot_flash_sec;
292 extern unsigned int boot_flash_type;
295 /*----------------------------------------------------------------------------
296 * SMSC9115 Ethernet from SMSC9118 family
297 *----------------------------------------------------------------------------
299 #if defined(CONFIG_CMD_NET)
301 #define CONFIG_DRIVER_SMC911X
302 #define CONFIG_DRIVER_SMC911X_32_BIT
303 #define CONFIG_DRIVER_SMC911X_BASE 0x2C000000
305 #endif /* (CONFIG_CMD_NET) */
311 #define CONFIG_BOOTP_SUBNETMASK 0x00000001
312 #define CONFIG_BOOTP_GATEWAY 0x00000002
313 #define CONFIG_BOOTP_HOSTNAME 0x00000004
314 #define CONFIG_BOOTP_BOOTPATH 0x00000010
316 #endif /* __CONFIG_H */