2 * Configuration settings for the TI OMAP3 EVM board.
4 * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
7 * Manikandan Pillai <mani.pillai@ti.com>
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * Manikandan Pillai <mani.pillai@ti.com>
14 * SPDX-License-Identifier: GPL-2.0+
17 #ifndef __OMAP3EVM_CONFIG_H
18 #define __OMAP3EVM_CONFIG_H
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/omap.h>
23 /* ----------------------------------------------------------------------------
24 * Supported U-Boot commands
25 * ----------------------------------------------------------------------------
28 #define CONFIG_CMD_JFFS2
30 #define CONFIG_CMD_NAND
32 /* ----------------------------------------------------------------------------
33 * Supported U-Boot features
34 * ----------------------------------------------------------------------------
36 #define CONFIG_SYS_LONGHELP
38 /* Display CPU and Board information */
39 #define CONFIG_DISPLAY_CPUINFO
40 #define CONFIG_DISPLAY_BOARDINFO
42 /* Allow to overwrite serial and ethaddr */
43 #define CONFIG_ENV_OVERWRITE
45 /* Add auto-completion support */
46 #define CONFIG_AUTO_COMPLETE
48 /* ----------------------------------------------------------------------------
50 * ----------------------------------------------------------------------------
55 #define CONFIG_GENERIC_MMC
56 #define CONFIG_OMAP_HSMMC
59 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
60 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
61 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
62 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
64 /* Partition tables */
65 #define CONFIG_EFI_PARTITION
66 #define CONFIG_DOS_PARTITION
70 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
71 * Enable CONFIG_USB_MUSB_UDD for Device functionalities.
73 #define CONFIG_USB_OMAP3
74 #define CONFIG_USB_MUSB_HCD
75 /* #define CONFIG_USB_MUSB_UDC */
78 #define CONFIG_SPL_NAND_SIMPLE
79 #define CONFIG_SPL_NAND_BASE
80 #define CONFIG_SPL_NAND_DRIVERS
81 #define CONFIG_SPL_NAND_ECC
82 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
83 #define CONFIG_SYS_NAND_PAGE_COUNT 64
84 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
85 #define CONFIG_SYS_NAND_OOBSIZE 64
86 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
87 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
88 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
90 #define CONFIG_SYS_NAND_ECCSIZE 512
91 #define CONFIG_SYS_NAND_ECCBYTES 3
92 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
93 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
94 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
97 * High level configuration options
99 #define CONFIG_OMAP /* This is TI OMAP core */
100 #define CONFIG_OMAP_GPIO
101 #define CONFIG_OMAP_COMMON
102 /* Common ARM Erratas */
103 #define CONFIG_ARM_ERRATA_454179
104 #define CONFIG_ARM_ERRATA_430973
105 #define CONFIG_ARM_ERRATA_621766
107 #define CONFIG_SDRC /* The chip has SDRC controller */
109 #define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
110 #define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
113 * Clock related definitions
115 #define V_OSCK 26000000 /* Clock output from T2 */
116 #define V_SCLK (V_OSCK >> 1)
119 * OMAP3 has 12 GP timers, they can be driven by the system clock
120 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
121 * This rate is divided by a local divisor.
123 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
124 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
126 /* Size of environment - 128KB */
127 #define CONFIG_ENV_SIZE (128 << 10)
129 /* Size of malloc pool */
130 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
133 * Physical Memory Map
134 * Note 1: CS1 may or may not be populated
135 * Note 2: SDRAM size is expected to be at least 32MB
137 #define CONFIG_NR_DRAM_BANKS 2
138 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
139 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
141 /* Limits for memtest */
142 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
143 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
144 0x01F00000) /* 31MB */
146 /* Default load address */
147 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
149 /* -----------------------------------------------------------------------------
151 * -----------------------------------------------------------------------------
155 * NS16550 Configuration
157 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
159 #define CONFIG_SYS_NS16550_SERIAL
160 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
161 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
164 * select serial console configuration
166 #define CONFIG_CONS_INDEX 1
167 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
168 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
169 #define CONFIG_BAUDRATE 115200
170 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
176 #define CONFIG_SYS_I2C
177 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
178 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
179 #define CONFIG_SYS_I2C_OMAP34XX
184 /* Monitor at start of flash - Reserve 2 sectors */
185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
187 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
189 /* Start location & size of environment */
190 #define ONENAND_ENV_OFFSET 0x260000
191 #define SMNAND_ENV_OFFSET 0x260000
193 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
198 /* Physical address to access NAND */
199 #define CONFIG_SYS_NAND_ADDR NAND_BASE
201 /* Physical address to access NAND at CS0 */
202 #define CONFIG_SYS_NAND_BASE NAND_BASE
204 /* Max number of NAND devices */
205 #define CONFIG_SYS_MAX_NAND_DEVICE 1
206 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
207 /* Timeout values (in ticks) */
208 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
209 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
211 /* Flash banks JFFS2 should use */
212 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
213 CONFIG_SYS_MAX_NAND_DEVICE)
215 #define CONFIG_SYS_JFFS2_MEM_NAND
216 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
217 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
219 #define CONFIG_JFFS2_NAND
220 /* nand device jffs2 lives on */
221 #define CONFIG_JFFS2_DEV "nand0"
222 /* Start of jffs2 partition */
223 #define CONFIG_JFFS2_PART_OFFSET 0x680000
224 /* Size of jffs2 partition */
225 #define CONFIG_JFFS2_PART_SIZE 0xf980000
230 #ifdef CONFIG_USB_OMAP3
232 #ifdef CONFIG_USB_MUSB_HCD
234 #define CONGIG_CMD_STORAGE
236 #ifdef CONFIG_USB_KEYBOARD
237 #define CONFIG_SYS_USB_EVENT_POLL
238 #define CONFIG_PREBOOT "usb start"
239 #endif /* CONFIG_USB_KEYBOARD */
241 #endif /* CONFIG_USB_MUSB_HCD */
243 #ifdef CONFIG_USB_MUSB_UDC
244 /* USB device configuration */
245 #define CONFIG_USB_DEVICE
246 #define CONFIG_USB_TTY
247 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
249 /* Change these to suit your needs */
250 #define CONFIG_USBD_VENDORID 0x0451
251 #define CONFIG_USBD_PRODUCTID 0x5678
252 #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
253 #define CONFIG_USBD_PRODUCT_NAME "EVM"
254 #endif /* CONFIG_USB_MUSB_UDC */
256 #endif /* CONFIG_USB_OMAP3 */
258 /* ----------------------------------------------------------------------------
260 * ----------------------------------------------------------------------------
262 #define CONFIG_SYS_MAXARGS 16 /* max args for a command */
264 #define CONFIG_MISC_INIT_R
266 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
267 #define CONFIG_SETUP_MEMORY_TAGS
268 #define CONFIG_INITRD_TAG
269 #define CONFIG_REVISION_TAG
271 /* Size of Console IO buffer */
272 #define CONFIG_SYS_CBSIZE 512
274 /* Size of print buffer */
275 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
276 sizeof(CONFIG_SYS_PROMPT) + 16)
278 /* Size of bootarg buffer */
279 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
281 #define CONFIG_BOOTFILE "uImage"
286 #if defined(CONFIG_CMD_NAND)
287 #define CONFIG_SYS_FLASH_BASE NAND_BASE
289 #define CONFIG_NAND_OMAP_GPMC
290 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
291 #elif defined(CONFIG_CMD_ONENAND)
292 #define CONFIG_SYS_FLASH_BASE ONENAND_MAP
293 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
296 #if !defined(CONFIG_ENV_IS_NOWHERE)
297 #if defined(CONFIG_CMD_NAND)
298 #define CONFIG_ENV_IS_IN_NAND
299 #elif defined(CONFIG_CMD_ONENAND)
300 #define CONFIG_ENV_IS_IN_ONENAND
301 #define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
303 #endif /* CONFIG_ENV_IS_NOWHERE */
305 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
307 #if defined(CONFIG_CMD_NET)
309 /* Ethernet (SMSC9115 from SMSC9118 family) */
310 #define CONFIG_SMC911X
311 #define CONFIG_SMC911X_32_BIT
312 #define CONFIG_SMC911X_BASE 0x2C000000
315 #define CONFIG_BOOTP_SUBNETMASK 0x00000001
316 #define CONFIG_BOOTP_GATEWAY 0x00000002
317 #define CONFIG_BOOTP_HOSTNAME 0x00000004
318 #define CONFIG_BOOTP_BOOTPATH 0x00000010
320 #endif /* CONFIG_CMD_NET */
322 /* Support for relocation */
323 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
324 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
325 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
326 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
327 CONFIG_SYS_INIT_RAM_SIZE - \
328 GENERATED_GBL_DATA_SIZE)
330 /* -----------------------------------------------------------------------------
332 * -----------------------------------------------------------------------------
334 #define CONFIG_SYS_NO_FLASH
336 /* Uncomment to define the board revision statically */
337 /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
339 /* Defines for SPL */
340 #define CONFIG_SPL_FRAMEWORK
341 #define CONFIG_SPL_TEXT_BASE 0x40200800
342 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
343 CONFIG_SPL_TEXT_BASE)
345 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
346 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
348 #define CONFIG_SPL_BOARD_INIT
349 #define CONFIG_SPL_SERIAL_SUPPORT
350 #define CONFIG_SPL_POWER_SUPPORT
351 #define CONFIG_SPL_OMAP3_ID_NAND
352 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
355 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
356 * 64 bytes before this address should be set aside for u-boot.img's
357 * header. That is 0x800FFFC0--0x80100000 should not be used for any
360 #define CONFIG_SYS_TEXT_BASE 0x80100000
361 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
362 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
364 /* -----------------------------------------------------------------------------
365 * Default environment
366 * -----------------------------------------------------------------------------
369 #define CONFIG_EXTRA_ENV_SETTINGS \
370 "loadaddr=0x82000000\0" \
373 "console=ttyO0,115200n8\0" \
374 "mmcargs=setenv bootargs console=${console} " \
375 "root=/dev/mmcblk0p2 rw " \
376 "rootfstype=ext3 rootwait\0" \
377 "nandargs=setenv bootargs console=${console} " \
378 "root=/dev/mtdblock4 rw " \
379 "rootfstype=jffs2\0" \
380 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
381 "bootscript=echo Running bootscript from mmc ...; " \
382 "source ${loadaddr}\0" \
383 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
384 "mmcboot=echo Booting from mmc ...; " \
386 "bootm ${loadaddr}\0" \
387 "nandboot=echo Booting from nand ...; " \
389 "onenand read ${loadaddr} 280000 400000; " \
390 "bootm ${loadaddr}\0" \
392 #define CONFIG_BOOTCOMMAND \
393 "mmc dev ${mmcdev}; if mmc rescan; then " \
394 "if run loadbootscript; then " \
397 "if run loaduimage; then " \
399 "else run nandboot; " \
402 "else run nandboot; fi"
404 #endif /* __OMAP3EVM_CONFIG_H */