2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
7 * Configuration settings for the TI OMAP3530 Beagle board.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/sizes.h>
33 * High Level Configuration Options
35 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
36 #define CONFIG_OMAP 1 /* in a TI OMAP core */
37 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
38 #define CONFIG_OMAP3430 1 /* which is in a 3430 */
39 #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
41 #include <asm/arch/cpu.h> /* get chip and board defs */
42 #include <asm/arch/omap3.h>
45 * Display CPU and Board information
47 #define CONFIG_DISPLAY_CPUINFO 1
48 #define CONFIG_DISPLAY_BOARDINFO 1
51 #define V_OSCK 26000000 /* Clock output from T2 */
52 #define V_SCLK (V_OSCK >> 1)
54 #undef CONFIG_USE_IRQ /* no support for IRQs */
55 #define CONFIG_MISC_INIT_R
57 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
58 #define CONFIG_SETUP_MEMORY_TAGS 1
59 #define CONFIG_INITRD_TAG 1
60 #define CONFIG_REVISION_TAG 1
63 * Size of malloc() pool
65 #define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
67 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
68 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
76 * NS16550 Configuration
78 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
80 #define CONFIG_SYS_NS16550
81 #define CONFIG_SYS_NS16550_SERIAL
82 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
83 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
86 * select serial console configuration
88 #define CONFIG_CONS_INDEX 3
89 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
90 #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
92 /* allow to overwrite serial and ethaddr */
93 #define CONFIG_ENV_OVERWRITE
94 #define CONFIG_BAUDRATE 115200
95 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
98 #define CONFIG_OMAP3_MMC 1
99 #define CONFIG_DOS_PARTITION 1
101 /* commands to include */
102 #include <config_cmd_default.h>
104 #define CONFIG_CMD_EXT2 /* EXT2 Support */
105 #define CONFIG_CMD_FAT /* FAT support */
106 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
107 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
108 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
109 #define MTDIDS_DEFAULT "nand0=nand"
110 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
111 "1920k(u-boot),128k(u-boot-env),"\
114 #define CONFIG_CMD_I2C /* I2C serial bus support */
115 #define CONFIG_CMD_MMC /* MMC support */
116 #define CONFIG_CMD_NAND /* NAND support */
118 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
119 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
120 #undef CONFIG_CMD_IMI /* iminfo */
121 #undef CONFIG_CMD_IMLS /* List all found images */
122 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
123 #undef CONFIG_CMD_NFS /* NFS support */
125 #define CONFIG_SYS_NO_FLASH
126 #define CONFIG_HARD_I2C 1
127 #define CONFIG_SYS_I2C_SPEED 100000
128 #define CONFIG_SYS_I2C_SLAVE 1
129 #define CONFIG_SYS_I2C_BUS 0
130 #define CONFIG_SYS_I2C_BUS_SELECT 1
131 #define CONFIG_DRIVER_OMAP34XX_I2C 1
136 #define CONFIG_TWL4030_POWER 1
137 #define CONFIG_TWL4030_LED 1
142 #define CONFIG_NAND_OMAP_GPMC
143 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
145 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
146 /* to access nand at */
148 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
150 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
152 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
154 #define CONFIG_JFFS2_NAND
155 /* nand device jffs2 lives on */
156 #define CONFIG_JFFS2_DEV "nand0"
157 /* start of jffs2 partition */
158 #define CONFIG_JFFS2_PART_OFFSET 0x680000
159 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
162 /* Environment information */
163 #define CONFIG_BOOTDELAY 10
165 #define CONFIG_EXTRA_ENV_SETTINGS \
166 "loadaddr=0x82000000\0" \
167 "console=ttyS2,115200n8\0" \
169 "dvimode=1024x768MR-16@60\0" \
170 "defaultdisplay=dvi\0" \
171 "mmcroot=/dev/mmcblk0p2 rw\0" \
172 "mmcrootfstype=ext3 rootwait\0" \
173 "nandroot=/dev/mtdblock4 rw\0" \
174 "nandrootfstype=jffs2\0" \
175 "mmcargs=setenv bootargs console=${console} " \
177 "omapfb.mode=dvi:${dvimode} " \
179 "omapdss.def_disp=${defaultdisplay} " \
181 "rootfstype=${mmcrootfstype}\0" \
182 "nandargs=setenv bootargs console=${console} " \
184 "omapfb.mode=dvi:${dvimode} " \
186 "omapdss.def_disp=${defaultdisplay} " \
187 "root=${nandroot} " \
188 "rootfstype=${nandrootfstype}\0" \
189 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
190 "bootscript=echo Running bootscript from mmc ...; " \
191 "source ${loadaddr}\0" \
192 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
193 "mmcboot=echo Booting from mmc ...; " \
195 "bootm ${loadaddr}\0" \
196 "nandboot=echo Booting from nand ...; " \
198 "nand read ${loadaddr} 280000 400000; " \
199 "bootm ${loadaddr}\0" \
201 #define CONFIG_BOOTCOMMAND \
202 "if mmc init; then " \
203 "if run loadbootscript; then " \
206 "if run loaduimage; then " \
208 "else run nandboot; " \
211 "else run nandboot; fi"
213 #define CONFIG_AUTO_COMPLETE 1
215 * Miscellaneous configurable options
217 #define V_PROMPT "OMAP3 beagleboard.org # "
219 #define CONFIG_SYS_LONGHELP /* undef to save memory */
220 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
221 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
222 #define CONFIG_SYS_PROMPT V_PROMPT
223 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
224 /* Print Buffer Size */
225 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
226 sizeof(CONFIG_SYS_PROMPT) + 16)
227 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
228 /* Boot Argument Buffer Size */
229 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
231 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
233 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
234 0x01F00000) /* 31MB */
236 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
240 * OMAP3 has 12 GP timers, they can be driven by the system clock
241 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
242 * This rate is divided by a local divisor.
244 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
245 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
246 #define CONFIG_SYS_HZ 1000
248 /*-----------------------------------------------------------------------
251 * The stack sizes are set up in start.S using the settings below
253 #define CONFIG_STACKSIZE SZ_128K /* regular stack */
254 #ifdef CONFIG_USE_IRQ
255 #define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
256 #define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
259 /*-----------------------------------------------------------------------
260 * Physical Memory Map
262 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
263 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
264 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
265 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
267 /* SDRAM Bank Allocation method */
270 /*-----------------------------------------------------------------------
271 * FLASH and environment organization
274 /* **** PISMO SUPPORT *** */
276 /* Configure the PISMO */
277 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
278 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
280 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
282 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
283 #define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
285 #define CONFIG_SYS_FLASH_BASE boot_flash_base
287 /* Monitor at start of flash */
288 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
289 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
291 #define CONFIG_ENV_IS_IN_NAND 1
292 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
293 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
295 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
296 #define CONFIG_ENV_OFFSET boot_flash_off
297 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
299 /*-----------------------------------------------------------------------
300 * CFI FLASH driver setup
302 /* timeout values are in ticks */
303 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
304 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
306 /* Flash banks JFFS2 should use */
307 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
308 CONFIG_SYS_MAX_NAND_DEVICE)
309 #define CONFIG_SYS_JFFS2_MEM_NAND
310 /* use flash_info[2] */
311 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
312 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
315 extern struct gpmc *gpmc_cfg;
316 extern unsigned int boot_flash_base;
317 extern volatile unsigned int boot_flash_env_addr;
318 extern unsigned int boot_flash_off;
319 extern unsigned int boot_flash_sec;
320 extern unsigned int boot_flash_type;
323 #endif /* __CONFIG_H */