2 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 #ifndef __CONFIGS_MXS_H__
20 #define __CONFIGS_MXS_H__
26 #if defined(CONFIG_MX23) && defined(CONFIG_MX28)
27 #error Select either CONFIG_MX23 or CONFIG_MX28 , never both!
28 #elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28)
29 #error Select one of CONFIG_MX23 or CONFIG_MX28 !
32 #include <asm/arch/regs-base.h>
34 #if defined(CONFIG_MX23)
35 #include <asm/arch/iomux-mx23.h>
36 #elif defined(CONFIG_MX28)
37 #include <asm/arch/iomux-mx28.h>
45 #define CONFIG_BOARD_EARLY_INIT_F
46 #define CONFIG_ARCH_MISC_INIT
49 #define CONFIG_SPL_NO_CPU_SUPPORT_CODE
50 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
51 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
54 #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
55 #define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
56 #define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
58 /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
59 #define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
60 #if defined(CONFIG_MX23)
61 #define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024)
62 #elif defined(CONFIG_MX28)
63 #define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
66 /* Point initial SP in SRAM so SPL can use it too. */
67 #define CONFIG_SYS_INIT_SP_OFFSET \
68 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
69 #define CONFIG_SYS_INIT_SP_ADDR \
70 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
73 * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
74 * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
75 * binary. In case there was more of this mess, 0x100 bytes are skipped.
77 * In case of a HAB boot, we cannot for some weird reason use the first 4KiB
78 * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST
79 * blocks, thus U-Boot starts at offset +8 KiB of DRAM start.
81 * As for the SPL, we must avoid the first 4 KiB as well, but we load the
82 * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
84 #define CONFIG_SYS_TEXT_BASE 0x40002000
85 #define CONFIG_SPL_TEXT_BASE 0x00001000
87 /* U-Boot general configuration */
88 #define CONFIG_SYS_LONGHELP
89 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
90 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
91 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
92 /* Boot argument buffer size */
93 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
94 #define CONFIG_CMDLINE_EDITING /* Command history etc */
97 #define CONFIG_CMDLINE_TAG
98 #define CONFIG_SETUP_MEMORY_TAGS
105 #define CONFIG_APBH_DMA
108 #define CONFIG_MXS_GPIO
111 * DUART Serial Driver.
112 * Conflicts with AUART driver which can be set by board.
114 #define CONFIG_PL011_SERIAL
115 #define CONFIG_PL011_CLOCK 24000000
116 #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
117 #define CONFIG_CONS_INDEX 0
118 /* Default baudrate can be overridden by board! */
119 #ifndef CONFIG_BAUDRATE
120 #define CONFIG_BAUDRATE 115200
123 /* FEC Ethernet on SoC */
124 #ifdef CONFIG_FEC_MXC
126 #ifndef CONFIG_ETHPRIME
127 #define CONFIG_ETHPRIME "FEC0"
129 #ifndef CONFIG_FEC_XCV_TYPE
130 #define CONFIG_FEC_XCV_TYPE RMII
135 #ifdef CONFIG_CMD_I2C
136 #define CONFIG_SYS_I2C
137 #define CONFIG_SYS_I2C_MXS
138 #define CONFIG_HARD_I2C
139 #ifndef CONFIG_SYS_I2C_SPEED
140 #define CONFIG_SYS_I2C_SPEED 400000
146 #define CONFIG_VIDEO_MXS
147 #define CONFIG_VIDEO_SW_CURSOR
148 #define CONFIG_VGA_AS_SINGLE_DEVICE
152 #ifdef CONFIG_CMD_MMC
154 #define CONFIG_GENERIC_MMC
155 #define CONFIG_BOUNCE_BUFFER
156 #define CONFIG_MXS_MMC
160 #ifdef CONFIG_CMD_NAND
161 #define CONFIG_NAND_MXS
162 #define CONFIG_SYS_MAX_NAND_DEVICE 1
163 #define CONFIG_SYS_NAND_BASE 0x60000000
164 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
168 #ifdef CONFIG_CMD_FUSE
169 #define CONFIG_MXS_OCOTP
173 #ifdef CONFIG_CMD_SPI
174 #define CONFIG_HARD_SPI
175 #define CONFIG_MXS_SPI
176 #define CONFIG_SPI_HALF_DUPLEX
180 #ifdef CONFIG_CMD_USB
181 #define CONFIG_USB_EHCI
182 #define CONFIG_USB_EHCI_MXS
183 #define CONFIG_EHCI_IS_TDI
186 #endif /* __CONFIGS_MXS_H__ */