2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6SX Sabresd board.
6 * SPDX-License-Identifier: GPL-2.0+
13 #include "mx6_common.h"
16 #define CONFIG_DISPLAY_CPUINFO
17 #define CONFIG_DISPLAY_BOARDINFO
20 #define CONFIG_SPL_LIBCOMMON_SUPPORT
21 #define CONFIG_SPL_MMC_SUPPORT
25 #define CONFIG_CMDLINE_TAG
26 #define CONFIG_SETUP_MEMORY_TAGS
27 #define CONFIG_INITRD_TAG
28 #define CONFIG_REVISION_TAG
29 #define CONFIG_SYS_GENERIC_BOARD
31 /* Size of malloc() pool */
32 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
34 #define CONFIG_BOARD_EARLY_INIT_F
35 #define CONFIG_MXC_GPIO
37 #define CONFIG_MXC_UART
38 #define CONFIG_MXC_UART_BASE UART1_BASE
40 /* allow to overwrite serial and ethaddr */
41 #define CONFIG_ENV_OVERWRITE
42 #define CONFIG_CONS_INDEX 1
43 #define CONFIG_BAUDRATE 115200
45 /* Command definition */
47 #define CONFIG_BOOTDELAY 3
49 #define CONFIG_LOADADDR 0x80800000
50 #define CONFIG_SYS_TEXT_BASE 0x87800000
52 #define CONFIG_EXTRA_ENV_SETTINGS \
56 "fdt_high=0xffffffff\0" \
57 "initrd_high=0xffffffff\0" \
58 "fdt_file=imx6sx-sdb.dtb\0" \
59 "fdt_addr=0x88000000\0" \
64 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
65 "mmcargs=setenv bootargs console=${console},${baudrate} " \
68 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
69 "bootscript=echo Running bootscript from mmc ...; " \
71 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
72 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
73 "mmcboot=echo Booting from mmc ...; " \
75 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
76 "if run loadfdt; then " \
77 "bootz ${loadaddr} - ${fdt_addr}; " \
79 "if test ${boot_fdt} = try; then " \
82 "echo WARN: Cannot load the DT; " \
88 "netargs=setenv bootargs console=${console},${baudrate} " \
90 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
91 "netboot=echo Booting from net ...; " \
93 "if test ${ip_dyn} = yes; then " \
94 "setenv get_cmd dhcp; " \
96 "setenv get_cmd tftp; " \
98 "${get_cmd} ${image}; " \
99 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
100 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
101 "bootz ${loadaddr} - ${fdt_addr}; " \
103 "if test ${boot_fdt} = try; then " \
106 "echo WARN: Cannot load the DT; " \
113 #define CONFIG_BOOTCOMMAND \
114 "mmc dev ${mmcdev};" \
115 "mmc dev ${mmcdev}; if mmc rescan; then " \
116 "if run loadbootscript; then " \
119 "if run loadimage; then " \
121 "else run netboot; " \
124 "else run netboot; fi"
126 /* Miscellaneous configurable options */
127 #define CONFIG_SYS_LONGHELP
128 #define CONFIG_SYS_HUSH_PARSER
129 #define CONFIG_AUTO_COMPLETE
130 #define CONFIG_SYS_CBSIZE 1024
132 #define CONFIG_SYS_MAXARGS 256
133 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
135 #define CONFIG_SYS_MEMTEST_START 0x80000000
136 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
138 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
140 #define CONFIG_CMDLINE_EDITING
141 #define CONFIG_STACKSIZE SZ_128K
143 /* Physical Memory Map */
144 #define CONFIG_NR_DRAM_BANKS 1
145 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
146 #define PHYS_SDRAM_SIZE SZ_1G
148 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
149 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
150 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
152 #define CONFIG_SYS_INIT_SP_OFFSET \
153 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
154 #define CONFIG_SYS_INIT_SP_ADDR \
155 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
157 /* MMC Configuration */
158 #define CONFIG_FSL_ESDHC
159 #define CONFIG_FSL_USDHC
160 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
163 #define CONFIG_CMD_MMC
164 #define CONFIG_GENERIC_MMC
165 #define CONFIG_BOUNCE_BUFFER
166 #define CONFIG_CMD_EXT2
167 #define CONFIG_CMD_FAT
168 #define CONFIG_DOS_PARTITION
171 #define CONFIG_CMD_I2C
172 #define CONFIG_SYS_I2C
173 #define CONFIG_SYS_I2C_MXC
174 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
175 #define CONFIG_SYS_I2C_SPEED 100000
179 #define CONFIG_POWER_I2C
180 #define CONFIG_POWER_PFUZE100
181 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
184 #define CONFIG_CMD_PING
185 #define CONFIG_CMD_DHCP
186 #define CONFIG_CMD_MII
187 #define CONFIG_CMD_NET
188 #define CONFIG_FEC_MXC
191 #define IMX_FEC_BASE ENET_BASE_ADDR
192 #define CONFIG_FEC_MXC_PHYADDR 0x1
194 #define CONFIG_FEC_XCV_TYPE RGMII
195 #define CONFIG_ETHPRIME "FEC"
197 #define CONFIG_PHYLIB
198 #define CONFIG_PHY_ATHEROS
201 #define CONFIG_CMD_USB
202 #ifdef CONFIG_CMD_USB
203 #define CONFIG_USB_EHCI
204 #define CONFIG_USB_EHCI_MX6
205 #define CONFIG_USB_STORAGE
206 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
207 #define CONFIG_USB_HOST_ETHER
208 #define CONFIG_USB_ETHER_ASIX
209 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
210 #define CONFIG_MXC_USB_FLAGS 0
211 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
214 #define CONFIG_CMD_PCI
215 #ifdef CONFIG_CMD_PCI
217 #define CONFIG_PCI_PNP
218 #define CONFIG_PCI_SCAN_SHOW
219 #define CONFIG_PCIE_IMX
220 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0)
221 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)
224 #define CONFIG_IMX6_THERMAL
226 #define CONFIG_CMD_FUSE
227 #if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
228 #define CONFIG_MXC_OCOTP
231 #define CONFIG_CMD_TIME
233 #define CONFIG_FSL_QSPI
235 #ifdef CONFIG_FSL_QSPI
236 #define CONFIG_CMD_SF
237 #define CONFIG_SPI_FLASH
238 #define CONFIG_SPI_FLASH_BAR
239 #define CONFIG_SPI_FLASH_SPANSION
240 #define CONFIG_SPI_FLASH_STMICRO
241 #define CONFIG_SYS_FSL_QSPI_LE
242 #define CONFIG_SYS_FSL_QSPI_AHB
243 #ifdef CONFIG_MX6SX_SABRESD_REVA
244 #define FSL_QSPI_FLASH_SIZE SZ_16M
246 #define FSL_QSPI_FLASH_SIZE SZ_32M
248 #define FSL_QSPI_FLASH_NUM 2
251 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
252 #define CONFIG_ENV_SIZE SZ_8K
253 #define CONFIG_ENV_IS_IN_MMC
255 #define CONFIG_OF_LIBFDT
256 #define CONFIG_CMD_BOOTZ
258 #ifndef CONFIG_SYS_DCACHE_OFF
259 #define CONFIG_CMD_CACHE
262 #define CONFIG_SYS_FSL_USDHC_NUM 3
263 #if defined(CONFIG_ENV_IS_IN_MMC)
264 #define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
267 #endif /* __CONFIG_H */