1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
5 * Configuration settings for the Freescale i.MX6SX Sabreauto board.
11 #include "mx6_common.h"
13 /* Size of malloc() pool */
14 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
16 #define CONFIG_MXC_UART
17 #define CONFIG_MXC_UART_BASE UART1_BASE
19 #define CONFIG_EXTRA_ENV_SETTINGS \
23 "fdt_high=0xffffffff\0" \
24 "initrd_high=0xffffffff\0" \
25 "fdt_file=imx6sx-sabreauto.dtb\0" \
26 "fdt_addr=0x88000000\0" \
31 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
32 "mmcargs=setenv bootargs console=${console},${baudrate} " \
35 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
36 "bootscript=echo Running bootscript from mmc ...; " \
38 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
39 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
40 "mmcboot=echo Booting from mmc ...; " \
42 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
43 "if run loadfdt; then " \
44 "bootz ${loadaddr} - ${fdt_addr}; " \
46 "if test ${boot_fdt} = try; then " \
49 "echo WARN: Cannot load the DT; " \
55 "netargs=setenv bootargs console=${console},${baudrate} " \
57 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
58 "netboot=echo Booting from net ...; " \
60 "if test ${ip_dyn} = yes; then " \
61 "setenv get_cmd dhcp; " \
63 "setenv get_cmd tftp; " \
65 "${get_cmd} ${image}; " \
66 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
67 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
68 "bootz ${loadaddr} - ${fdt_addr}; " \
70 "if test ${boot_fdt} = try; then " \
73 "echo WARN: Cannot load the DT; " \
80 #define CONFIG_BOOTCOMMAND \
81 "mmc dev ${mmcdev};" \
82 "mmc dev ${mmcdev}; if mmc rescan; then " \
83 "if run loadbootscript; then " \
86 "if run loadimage; then " \
88 "else run netboot; " \
91 "else run netboot; fi"
93 /* Miscellaneous configurable options */
94 #define CONFIG_SYS_MEMTEST_START 0x80000000
95 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
97 /* Physical Memory Map */
98 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
100 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
101 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
102 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
104 #define CONFIG_SYS_INIT_SP_OFFSET \
105 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
106 #define CONFIG_SYS_INIT_SP_ADDR \
107 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
109 /* MMC Configuration */
110 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
113 #define CONFIG_SYS_I2C_MXC
114 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
115 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
116 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
117 #define CONFIG_SYS_I2C_SPEED 100000
120 #define CONFIG_SYS_MAX_NAND_DEVICE 1
121 #define CONFIG_SYS_NAND_BASE 0x40000000
122 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
123 #define CONFIG_SYS_NAND_ONFI_DETECTION
125 /* DMA stuff, needed for GPMI/MXS NAND support */
129 #define CONFIG_FEC_MXC
131 #define IMX_FEC_BASE ENET2_BASE_ADDR
132 #define CONFIG_FEC_MXC_PHYADDR 0x0
134 #define CONFIG_FEC_XCV_TYPE RGMII
135 #define CONFIG_ETHPRIME "FEC"
137 #define CONFIG_PHY_ATHEROS
139 #ifdef CONFIG_CMD_USB
140 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
141 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
142 #define CONFIG_MXC_USB_FLAGS 0
143 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
146 #define CONFIG_IMX_THERMAL
148 #ifdef CONFIG_FSL_QSPI
149 #define CONFIG_SYS_FSL_QSPI_AHB
150 #define CONFIG_SF_DEFAULT_BUS 0
151 #define CONFIG_SF_DEFAULT_CS 0
152 #define CONFIG_SF_DEFAULT_SPEED 40000000
153 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
154 #define FSL_QSPI_FLASH_SIZE SZ_32M
155 #define FSL_QSPI_FLASH_NUM 2
158 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
159 #define CONFIG_ENV_SIZE SZ_8K
161 #define CONFIG_SYS_FSL_USDHC_NUM 2
162 #if defined(CONFIG_ENV_IS_IN_MMC)
163 #define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/
166 #endif /* __CONFIG_H */