2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6Q Sabre Lite board.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #define CONFIG_SYS_MX6_HCLK 24000000
27 #define CONFIG_SYS_MX6_CLK32 32768
28 #define CONFIG_DISPLAY_CPUINFO
29 #define CONFIG_DISPLAY_BOARDINFO
31 #define CONFIG_MACH_TYPE 3769
33 #include <asm/arch/imx-regs.h>
35 #define CONFIG_CMDLINE_TAG
36 #define CONFIG_SETUP_MEMORY_TAGS
37 #define CONFIG_INITRD_TAG
38 #define CONFIG_REVISION_TAG
40 /* Size of malloc() pool */
41 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
43 #define CONFIG_ARCH_CPU_INIT
44 #define CONFIG_BOARD_EARLY_INIT_F
45 #define CONFIG_MXC_GPIO
47 #define CONFIG_MXC_UART
48 #define CONFIG_MXC_UART_BASE UART2_BASE
52 #define CONFIG_SPI_FLASH
53 #define CONFIG_SPI_FLASH_SST
54 #define CONFIG_MXC_SPI
55 #define CONFIG_SF_DEFAULT_BUS 0
56 #define CONFIG_SF_DEFAULT_CS (0|(GPIO_NUMBER(3, 19)<<8))
57 #define CONFIG_SF_DEFAULT_SPEED 25000000
58 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
62 #define CONFIG_FSL_ESDHC
63 #define CONFIG_FSL_USDHC
64 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
65 #define CONFIG_SYS_FSL_USDHC_NUM 2
68 #define CONFIG_CMD_MMC
69 #define CONFIG_GENERIC_MMC
70 #define CONFIG_CMD_EXT2
71 #define CONFIG_CMD_FAT
72 #define CONFIG_DOS_PARTITION
74 #define CONFIG_CMD_PING
75 #define CONFIG_CMD_DHCP
76 #define CONFIG_CMD_MII
77 #define CONFIG_CMD_NET
78 #define CONFIG_FEC_MXC
80 #define IMX_FEC_BASE ENET_BASE_ADDR
81 #define CONFIG_FEC_XCV_TYPE RGMII
82 #define CONFIG_ETHPRIME "FEC"
83 #define CONFIG_FEC_MXC_PHYADDR 6
85 #define CONFIG_PHY_MICREL
88 #define CONFIG_CMD_USB
89 #define CONFIG_CMD_FAT
90 #define CONFIG_USB_EHCI
91 #define CONFIG_USB_EHCI_MX6
92 #define CONFIG_USB_STORAGE
93 #define CONFIG_USB_HOST_ETHER
94 #define CONFIG_USB_ETHER_ASIX
95 #define CONFIG_USB_ETHER_SMSC95XX
96 #define CONFIG_MXC_USB_PORT 1
97 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
98 #define CONFIG_MXC_USB_FLAGS 0
100 /* allow to overwrite serial and ethaddr */
101 #define CONFIG_ENV_OVERWRITE
102 #define CONFIG_CONS_INDEX 1
103 #define CONFIG_BAUDRATE 115200
104 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
106 /* Command definition */
107 #include <config_cmd_default.h>
109 #undef CONFIG_CMD_IMLS
111 #define CONFIG_BOOTDELAY 3
113 #define CONFIG_LOADADDR 0x10800000
114 #define CONFIG_SYS_TEXT_BASE 0x17800000
116 #define CONFIG_EXTRA_ENV_SETTINGS \
117 "script=boot.scr\0" \
119 "console=ttymxc3\0" \
120 "fdt_high=0xffffffff\0" \
121 "initrd_high=0xffffffff\0" \
124 "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
125 "mmcargs=setenv bootargs console=${console},${baudrate} " \
126 "root=${mmcroot}\0" \
128 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
129 "bootscript=echo Running bootscript from mmc ...; " \
131 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
132 "mmcboot=echo Booting from mmc ...; " \
135 "netargs=setenv bootargs console=${console},${baudrate} " \
137 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
138 "netboot=echo Booting from net ...; " \
140 "dhcp ${uimage}; bootm\0" \
142 #define CONFIG_BOOTCOMMAND \
143 "mmc dev ${mmcdev};" \
144 "if mmc rescan ${mmcdev}; then " \
145 "if run loadbootscript; then " \
148 "if run loaduimage; then " \
150 "else run netboot; " \
153 "else run netboot; fi"
155 #define CONFIG_ARP_TIMEOUT 200UL
157 /* Miscellaneous configurable options */
158 #define CONFIG_SYS_LONGHELP
159 #define CONFIG_SYS_HUSH_PARSER
160 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
161 #define CONFIG_SYS_PROMPT "MX6QSABRELITE U-Boot > "
162 #define CONFIG_AUTO_COMPLETE
163 #define CONFIG_SYS_CBSIZE 256
165 /* Print Buffer Size */
166 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
167 #define CONFIG_SYS_MAXARGS 16
168 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
170 #define CONFIG_SYS_MEMTEST_START 0x10000000
171 #define CONFIG_SYS_MEMTEST_END 0x10010000
173 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
174 #define CONFIG_SYS_HZ 1000
176 #define CONFIG_CMDLINE_EDITING
177 #define CONFIG_STACKSIZE (128 * 1024)
179 /* Physical Memory Map */
180 #define CONFIG_NR_DRAM_BANKS 1
181 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
182 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
184 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
185 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
186 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
188 #define CONFIG_SYS_INIT_SP_OFFSET \
189 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
190 #define CONFIG_SYS_INIT_SP_ADDR \
191 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
193 /* FLASH and environment organization */
194 #define CONFIG_SYS_NO_FLASH
196 #define CONFIG_ENV_SIZE (8 * 1024)
198 #define CONFIG_ENV_IS_IN_MMC
199 /* #define CONFIG_ENV_IS_IN_SPI_FLASH */
201 #if defined(CONFIG_ENV_IS_IN_MMC)
202 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
203 #define CONFIG_SYS_MMC_ENV_DEV 0
204 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
205 #define CONFIG_ENV_OFFSET (768 * 1024)
206 #define CONFIG_ENV_SECT_SIZE (8 * 1024)
207 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
208 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
209 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
210 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
213 #define CONFIG_OF_LIBFDT
215 #define CONFIG_SYS_DCACHE_OFF
217 #endif /* __CONFIG_H */