1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 * Jason Liu <r64343@freescale.com>
6 * Configuration settings for Freescale MX53 low cost board.
12 #include <asm/arch/imx-regs.h>
14 #define CONSOLE_DEV "ttymxc0"
16 #define CONFIG_CMDLINE_TAG
17 #define CONFIG_SETUP_MEMORY_TAGS
18 #define CONFIG_INITRD_TAG
20 #define CONFIG_SYS_FSL_CLK
22 /* Size of malloc() pool */
23 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
25 #define CONFIG_HW_WATCHDOG
26 #define CONFIG_IMX_WATCHDOG
27 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000
29 #define CONFIG_MISC_INIT_R
30 #define CONFIG_BOARD_LATE_INIT
31 #define CONFIG_REVISION_TAG
33 #define CONFIG_MXC_UART
34 #define CONFIG_MXC_UART_BASE UART1_BASE
37 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
38 #define CONFIG_SYS_FSL_ESDHC_NUM 2
42 #define CONFIG_FEC_MXC
43 #define IMX_FEC_BASE FEC_BASE_ADDR
44 #define CONFIG_FEC_MXC_PHYADDR 0x1F
47 #define CONFIG_USB_EHCI_MX5
48 #define CONFIG_USB_HOST_ETHER
49 #define CONFIG_USB_ETHER_ASIX
50 #define CONFIG_USB_ETHER_MCS7830
51 #define CONFIG_USB_ETHER_SMSC95XX
52 #define CONFIG_MXC_USB_PORT 1
53 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
54 #define CONFIG_MXC_USB_FLAGS 0
56 #define CONFIG_SYS_RTC_BUS_NUM 2
57 #define CONFIG_SYS_I2C_RTC_ADDR 0x30
60 #define CONFIG_SYS_I2C
61 #define CONFIG_SYS_I2C_MXC
62 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
63 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
64 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
68 #define CONFIG_POWER_I2C
69 #define CONFIG_DIALOG_POWER
70 #define CONFIG_POWER_FSL
71 #define CONFIG_POWER_FSL_MC13892
72 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
73 #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
75 /* allow to overwrite serial and ethaddr */
76 #define CONFIG_ENV_OVERWRITE
77 #define CONFIG_BAUDRATE 115200
79 /* Command definition */
81 #define CONFIG_ETHPRIME "FEC0"
83 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
85 #define PPD_CONFIG_NFS \
86 "nfsserver=192.168.252.95\0" \
87 "gatewayip=192.168.252.95\0" \
88 "netmask=255.255.255.0\0" \
89 "ipaddr=192.168.252.99\0" \
92 "nfsroot=/opt/springdale/rd\0" \
93 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
94 "${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \
95 "choose_ip=if test $use_dhcp = 1; then set kern_ipconf ip=dhcp; " \
96 "set getcmd dhcp; else set kern_ipconf " \
97 "ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \
98 "set getcmd tftp; fi\0" \
99 "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \
100 "${nfsserver}:${image}; bootm ${loadaddr}\0" \
102 #define CONFIG_EXTRA_ENV_SETTINGS \
104 "image=/boot/fitImage\0" \
105 "fdt_high=0xffffffff\0" \
108 "rootdev=mmcblk0p\0" \
109 "quiet=quiet loglevel=0\0" \
110 "console=" CONSOLE_DEV "\0" \
112 "setargs=setenv bootargs ${lvds} jtag=on mem=2G " \
113 "vt.global_cursor_default=0 bootcause=${bootcause} ${quiet} " \
114 "console=${console} ${rtc_status}\0" \
115 "bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \
116 "rootwait ${bootargs}\0" \
117 "doquiet=if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
118 "then setenv quiet; fi\0" \
119 "hasfirstboot=ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
120 "/boot/bootcause/firstboot\0" \
121 "swappartitions=setexpr partnum 3 - ${partnum}\0" \
124 "msg=\"Monitor failed to start. " \
125 "Try again, or contact GE Service for support.\"; " \
127 "setenv stdout vga; " \
128 "echo \"\n\n\n\n \" $msg; " \
129 "setenv stdout serial; " \
130 "mw.b 0x7000A000 0xbc; " \
131 "mw.b 0x7000A001 0x00; " \
132 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
135 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
136 "run hasfirstboot || setenv partnum 0; " \
137 "if test ${partnum} != 0; then " \
138 "setenv bootcause REVERT; " \
139 "run swappartitions loadimage doboot; " \
141 "run failbootcmd\0" \
143 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
145 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \
147 "run bootargs_emmc; " \
148 "bootm ${loadaddr}\0" \
150 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
151 "run loadimage || run swappartitions && run loadimage || " \
152 "setenv partnum 0 && echo MISSING IMAGE;" \
154 "run failbootcmd\0" \
156 "lcd:800x480-24@60,monitor=lcd\0" \
158 #define CONFIG_MMCBOOTCOMMAND \
159 "if mmc dev ${devnum}; then " \
164 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
166 #define CONFIG_ARP_TIMEOUT 200UL
168 /* Miscellaneous configurable options */
169 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
171 #define CONFIG_SYS_MAXARGS 48 /* max number of command args */
172 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
174 #define CONFIG_SYS_MEMTEST_START 0x70000000
175 #define CONFIG_SYS_MEMTEST_END 0x70010000
177 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
179 /* Physical Memory Map */
180 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
181 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
182 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
183 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
184 #define PHYS_SDRAM_SIZE (gd->ram_size)
186 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
187 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
188 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
190 #define CONFIG_SYS_INIT_SP_OFFSET \
191 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
192 #define CONFIG_SYS_INIT_SP_ADDR \
193 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
195 /* FLASH and environment organization */
196 #define CONFIG_ENV_OFFSET (12 * 64 * 1024)
197 #define CONFIG_ENV_SIZE (10 * 1024)
198 #define CONFIG_SYS_MMC_ENV_DEV 0
200 #define CONFIG_CMD_FUSE
201 #define CONFIG_FSL_IIM
203 #define CONFIG_SYS_I2C_SPEED 100000
206 #define CONFIG_SYS_NUM_I2C_BUSES 9
207 #define CONFIG_SYS_I2C_MAX_HOPS 1
208 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
209 {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
210 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
211 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
212 {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
213 {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
214 {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
215 {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
216 {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
221 /* Backlight Control */
222 #define CONFIG_PWM_IMX
223 #define CONFIG_IMX6_PWM_PER_CLK 66666000
225 /* Framebuffer and LCD */
227 #define CONFIG_VIDEO_IPUV3
230 #endif /* __CONFIG_H */