2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
6 * Richard Woodruff <r-woodruff2@ti.com>
7 * Kshitij Gupta <kshitij@ti.com>
9 * Configuration settings for the Freescale i.MX31 PDK board.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/imx-regs.h>
19 /* High Level Configuration Options */
20 #define CONFIG_MX31 /* This is a mx31 */
22 #define CONFIG_DISPLAY_CPUINFO
23 #define CONFIG_DISPLAY_BOARDINFO
25 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
26 #define CONFIG_SETUP_MEMORY_TAGS
27 #define CONFIG_INITRD_TAG
29 #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
32 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
33 #define CONFIG_SPL_MAX_SIZE 2048
34 #define CONFIG_SPL_NAND_SUPPORT
35 #define CONFIG_SPL_LIBGENERIC_SUPPORT
36 #define CONFIG_SPL_SERIAL_SUPPORT
38 #define CONFIG_SPL_TEXT_BASE 0x87dc0000
39 #define CONFIG_SYS_TEXT_BASE 0x87e00000
41 #ifndef CONFIG_SPL_BUILD
42 #define CONFIG_SKIP_LOWLEVEL_INIT
46 * Size of malloc() pool
48 #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
54 #define CONFIG_MXC_UART
55 #define CONFIG_MXC_UART_BASE UART1_BASE
56 #define CONFIG_MXC_GPIO
58 #define CONFIG_HARD_SPI
59 #define CONFIG_MXC_SPI
60 #define CONFIG_DEFAULT_SPI_BUS 1
61 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
65 #define CONFIG_POWER_SPI
66 #define CONFIG_POWER_FSL
67 #define CONFIG_FSL_PMIC_BUS 1
68 #define CONFIG_FSL_PMIC_CS 2
69 #define CONFIG_FSL_PMIC_CLK 1000000
70 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
71 #define CONFIG_FSL_PMIC_BITLEN 32
72 #define CONFIG_RTC_MC13XXX
74 /* allow to overwrite serial and ethaddr */
75 #define CONFIG_ENV_OVERWRITE
76 #define CONFIG_CONS_INDEX 1
77 #define CONFIG_BAUDRATE 115200
79 /***********************************************************
81 ***********************************************************/
82 #define CONFIG_CMD_DATE
83 #define CONFIG_CMD_NAND
85 #define CONFIG_BOARD_LATE_INIT
87 #define CONFIG_BOOTDELAY 1
89 #define CONFIG_EXTRA_ENV_SETTINGS \
90 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
91 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
92 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
93 "bootcmd=run bootcmd_net\0" \
94 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
95 "tftpboot 0x81000000 uImage-mx31; bootm\0" \
96 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
97 "nand erase 0x0 0x40000; " \
98 "nand write 0x81000000 0x0 0x40000\0"
100 #define CONFIG_SMC911X
101 #define CONFIG_SMC911X_BASE 0xB6000000
102 #define CONFIG_SMC911X_32_BIT
105 * Miscellaneous configurable options
107 #define CONFIG_SYS_LONGHELP /* undef to save memory */
108 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
109 /* max number of command args */
110 #define CONFIG_SYS_MAXARGS 16
111 /* Boot Argument Buffer Size */
112 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
114 /* memtest works on */
115 #define CONFIG_SYS_MEMTEST_START 0x80000000
116 #define CONFIG_SYS_MEMTEST_END 0x80010000
118 /* default load address */
119 #define CONFIG_SYS_LOAD_ADDR 0x81000000
121 #define CONFIG_CMDLINE_EDITING
123 /*-----------------------------------------------------------------------
124 * Physical Memory Map
126 #define CONFIG_NR_DRAM_BANKS 1
127 #define PHYS_SDRAM_1 CSD0_BASE
128 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
129 #define CONFIG_BOARD_EARLY_INIT_F
131 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
132 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
133 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
134 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
135 GENERATED_GBL_DATA_SIZE)
136 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
137 CONFIG_SYS_INIT_RAM_SIZE)
139 /*-----------------------------------------------------------------------
140 * FLASH and environment organization
142 /* No NOR flash present */
143 #define CONFIG_SYS_NO_FLASH
145 #define CONFIG_ENV_IS_IN_NAND
146 #define CONFIG_ENV_OFFSET 0x40000
147 #define CONFIG_ENV_OFFSET_REDUND 0x60000
148 #define CONFIG_ENV_SIZE (128 * 1024)
153 #define CONFIG_NAND_MXC
154 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
155 #define CONFIG_SYS_MAX_NAND_DEVICE 1
156 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
157 #define CONFIG_MXC_NAND_HWECC
158 #define CONFIG_SYS_NAND_LARGEPAGE
160 /* NAND configuration for the NAND_SPL */
162 /* Start copying real U-Boot from the second page */
163 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
164 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
165 /* Load U-Boot to this address */
166 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
167 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
169 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
170 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
171 #define CONFIG_SYS_NAND_PAGE_COUNT 64
172 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
173 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
175 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
176 #define CCM_CCMR_SETUP 0x074B0BF5
177 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
178 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
179 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
180 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
181 #define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
184 #define ESDMISC_MDDR_SETUP 0x00000004
185 #define ESDMISC_MDDR_RESET_DL 0x0000000c
186 #define ESDCFG0_MDDR_SETUP 0x006ac73a
188 #define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
189 #define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
190 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
191 #define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
192 #define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
193 #define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
194 #define ESDCTL_RW ESDCTL_SETTINGS
196 #endif /* __CONFIG_H */