3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
33 #define CONFIG_MPC8260 1
34 #define CONFIG_MUAS3001 1
36 #define CONFIG_CPM2 1 /* Has a CPM2 */
38 /* Do boardspecific init */
39 #define CONFIG_BOARD_EARLY_INIT_R 1
42 #define CONFIG_WATCHDOG 1
45 * Select serial console configuration
47 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
48 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
51 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
52 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
53 #undef CONFIG_CONS_NONE /* It's not on external UART */
54 #if defined(CONFIG_MUAS_DEV_BOARD)
55 #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
57 #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
61 * Select ethernet configuration
63 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
64 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
67 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
68 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
71 #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
72 #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
73 #undef CONFIG_ETHER_NONE /* No external Ethernet */
75 #define CONFIG_ETHER_INDEX 1
76 #define CONFIG_ETHER_ON_FCC1
83 # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
84 # define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
86 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
88 # define CFG_CPMFCR_RAMTYPE (0)
89 /* know on local Bus */
90 /* define CFG_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) */
92 * - Enable Full Duplex in FSMR
94 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
96 #define CONFIG_MII /* MII PHY management */
97 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
98 # define CFG_PHY_ADDR 1
100 * GPIO pins used for bit-banged MII communications
102 #define MDIO_PORT 0 /* Port A */
104 #define CFG_MDIO_PIN 0x00200000 /* PA10 */
105 #define CFG_MDC_PIN 0x00400000 /* PA9 */
107 #define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
108 #define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
109 #define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
111 #define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
112 else iop->pdat &= ~CFG_MDIO_PIN
114 #define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
115 else iop->pdat &= ~CFG_MDC_PIN
117 #define MIIDELAY udelay(1)
119 #ifndef CONFIG_8260_CLKIN
120 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
123 #define CONFIG_BAUDRATE 115200
126 * Command line configuration.
128 #include <config_cmd_default.h>
130 #define CONFIG_CMD_ECHO
131 #define CONFIG_CMD_IMMAP
132 #define CONFIG_CMD_MII
133 #define CONFIG_CMD_PING
134 #define CONFIG_CMD_I2C
137 * Default environment settings
139 #define CONFIG_EXTRA_ENV_SETTINGS \
141 "u-boot_addr_r=100000\0" \
142 "kernel_addr_r=200000\0" \
143 "fdt_addr_r=400000\0" \
144 "rootpath=/opt/eldk/ppc_6xx\0" \
145 "u-boot=muas3001/u-boot.bin\0" \
146 "bootfile=muas3001/uImage\0" \
147 "fdt_file=muas3001/muas3001.dtb\0" \
148 "ramdisk_file=uRamdisk\0" \
149 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
150 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
151 "cp.b ${u-boot_addr_r} ff000000 ${filesize};" \
152 "prot on ff000000 ff03ffff\0" \
153 "ramargs=setenv bootargs root=/dev/ram rw\0" \
154 "nfsargs=setenv bootargs root=/dev/nfs rw " \
155 "nfsroot=${serverip}:${rootpath}\0" \
156 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
157 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
158 "addip=setenv bootargs ${bootargs} " \
159 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
160 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
161 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
162 "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \
163 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
164 "net_self=tftp ${kernel_addr_r} ${bootfile}; " \
165 "tftp ${fdt_addr_r} ${fdt_file}; " \
166 "tftp ${ramdisk_addr} ${ramdisk_file}; " \
167 "run ramargs addip; " \
168 "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \
169 "ramdisk_addr=ff210000\0" \
170 "kernel_addr=ff050000\0" \
171 "fdt_addr=ff200000\0" \
172 "flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \
173 " ${ramdisk_addr} ${fdt_addr}\0" \
174 "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \
175 " ${ramdisk_file};" \
176 "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \
177 "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \
179 "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \
180 "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \
181 "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \
184 #define CONFIG_BOOTCOMMAND "run net_nfs"
185 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
188 * Miscellaneous configurable options
190 #define CFG_HUSH_PARSER
191 #define CFG_PROMPT_HUSH_PS2 "> "
192 #define CFG_LONGHELP /* undef to save memory */
193 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
194 #if defined(CONFIG_CMD_KGDB)
195 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
197 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
199 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
200 #define CFG_MAXARGS 16 /* max number of command args */
201 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
203 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
204 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
206 #define CFG_LOAD_ADDR 0x100000 /* default load address */
208 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
210 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
212 #define CFG_SDRAM_BASE 0x00000000
213 #define CFG_FLASH_BASE 0xFF000000
214 #define CFG_FLASH_SIZE 32
215 #define CFG_FLASH_CFI
216 #define CONFIG_FLASH_CFI_DRIVER
217 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
218 #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
220 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
222 #define CFG_MONITOR_BASE TEXT_BASE
223 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
227 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
229 #define CFG_ENV_IS_IN_FLASH
231 #ifdef CFG_ENV_IS_IN_FLASH
232 #define CFG_ENV_SECT_SIZE 0x10000
233 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
234 #endif /* CFG_ENV_IS_IN_FLASH */
239 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
240 #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
241 #define CFG_I2C_SLAVE 0x7F
243 #define CFG_IMMR 0xF0000000
244 #define CFG_DEFAULT_IMMR 0x0F010000
246 #define CFG_INIT_RAM_ADDR CFG_IMMR
247 #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
248 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
249 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
250 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
252 /* Hard reset configuration word */
253 #define CFG_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */
256 #define CFG_HRCW_SLAVE1 0
257 #define CFG_HRCW_SLAVE2 0
258 #define CFG_HRCW_SLAVE3 0
259 #define CFG_HRCW_SLAVE4 0
260 #define CFG_HRCW_SLAVE5 0
261 #define CFG_HRCW_SLAVE6 0
262 #define CFG_HRCW_SLAVE7 0
264 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
265 #define BOOTFLAG_WARM 0x02 /* Software reboot */
267 #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
268 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
270 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
271 #if defined(CONFIG_CMD_KGDB)
272 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
275 #define CFG_HID0_INIT 0
276 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
280 #define CFG_SIUMCR 0x00200000
281 #define CFG_BCR 0x004c0000
284 /*-----------------------------------------------------------------------
285 * SYPCR - System Protection Control 4-35
286 * SYPCR can only be written once after reset!
287 *-----------------------------------------------------------------------
288 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
290 #if defined(CONFIG_WATCHDOG)
291 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
292 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
294 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
295 SYPCR_SWRI|SYPCR_SWP)
296 #endif /* CONFIG_WATCHDOG */
298 /*-----------------------------------------------------------------------
299 * RMR - Reset Mode Register 5-5
300 *-----------------------------------------------------------------------
301 * turn on Checkstop Reset Enable
305 /*-----------------------------------------------------------------------
306 * TMCNTSC - Time Counter Status and Control 4-40
307 *-----------------------------------------------------------------------
308 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
309 * and enable Time Counter
311 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
313 /*-----------------------------------------------------------------------
314 * PISCR - Periodic Interrupt Status and Control 4-42
315 *-----------------------------------------------------------------------
316 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
319 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
321 /*-----------------------------------------------------------------------
322 * RCCR - RISC Controller Configuration 13-7
323 *-----------------------------------------------------------------------
328 * Init Memory Controller:
330 * Bank Bus Machine PortSz Device
331 * ---- --- ------- ------ ------
332 * 0 60x GPCM 32 bit FLASH
333 * 1 60x SDRAM 64 bit SDRAM
334 * 4 60x GPCM 16 bit I/O Ctrl
339 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
344 #define CFG_OR0_PRELIM (0xff000020)
346 /* Bank 1 - 60x bus SDRAM
348 #define CFG_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
350 #define CFG_MPTPR 0x2800
352 /*-----------------------------------------------------------------------------
353 * Address for Mode Register Set (MRS) command
354 *-----------------------------------------------------------------------------
356 #define CFG_MRS_OFFS 0x00000110
357 #define CFG_PSRT 0x13
359 #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
364 #define CFG_OR1_PRELIM CFG_OR1_LITTLE
366 /* SDRAM initialization values
368 #define CFG_OR1_LITTLE ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
370 ORxS_ROWST_PBI1_A7 |\
373 #define CFG_PSDMR_LITTLE 0x004b36a3
375 #define CFG_OR1_BIG ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
377 ORxS_ROWST_PBI1_A4 |\
380 #define CFG_PSDMR_BIG 0x014f36a3
382 /* IO on CS4 initialization values
384 #define CFG_IO_BASE 0xc0000000
385 #define CFG_IO_SIZE 1
387 #define CFG_BR4_PRELIM ((CFG_IO_BASE & BRx_BA_MSK) |\
388 BRx_PS_32 | BRx_MS_GPCM_L | BRx_V)
390 #define CFG_OR4_PRELIM (0xfff80020)
392 #define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
394 /* pass open firmware flat tree */
395 #define CONFIG_OF_LIBFDT 1
396 #define CONFIG_OF_BOARD_SETUP 1
398 #define OF_CPU "PowerPC,8270@0"
399 #define OF_SOC "soc@f0000000"
400 #define OF_TBCLK (bd->bi_busfreq / 4)
401 #if defined(CONFIG_MUAS_DEV_BOARD)
402 #define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
404 #define OF_STDOUT_PATH "/soc/cpm/serial@11a80"
407 #endif /* __CONFIG_H */