3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
33 #define CONFIG_MPC8260 1
34 #define CONFIG_MUAS3001 1
36 #define CONFIG_CPM2 1 /* Has a CPM2 */
38 /* Do boardspecific init */
39 #define CONFIG_BOARD_EARLY_INIT_R 1
42 #define CONFIG_WATCHDOG 1
45 * Select serial console configuration
47 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
48 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
51 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
52 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
53 #undef CONFIG_CONS_NONE /* It's not on external UART */
54 #if defined(CONFIG_MUAS_DEV_BOARD)
55 #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
57 #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
61 * Select ethernet configuration
63 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
64 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
67 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
68 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
71 #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
72 #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
73 #undef CONFIG_ETHER_NONE /* No external Ethernet */
75 #define CONFIG_ETHER_INDEX 1
76 #define CONFIG_ETHER_ON_FCC1
77 #define CONFIG_HAS_ETH0
84 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
85 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
87 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
89 # define CONFIG_SYS_CPMFCR_RAMTYPE (0)
90 /* know on local Bus */
91 /* define CONFIG_SYS_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) */
93 * - Enable Full Duplex in FSMR
95 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
97 #define CONFIG_MII /* MII PHY management */
98 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
99 # define CONFIG_SYS_PHY_ADDR 1
101 * GPIO pins used for bit-banged MII communications
103 #define MDIO_PORT 0 /* Port A */
105 #define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */
106 #define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */
108 #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
109 #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
110 #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
112 #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
113 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
115 #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
116 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
118 #define MIIDELAY udelay(1)
120 #ifndef CONFIG_8260_CLKIN
121 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
124 #define CONFIG_BAUDRATE 115200
127 * Command line configuration.
129 #include <config_cmd_default.h>
131 #define CONFIG_CMD_DTT
132 #define CONFIG_CMD_ECHO
133 #define CONFIG_CMD_IMMAP
134 #define CONFIG_CMD_MII
135 #define CONFIG_CMD_PING
136 #define CONFIG_CMD_I2C
139 * Default environment settings
141 #define CONFIG_EXTRA_ENV_SETTINGS \
143 "u-boot_addr_r=100000\0" \
144 "kernel_addr_r=200000\0" \
145 "fdt_addr_r=400000\0" \
146 "rootpath=/opt/eldk/ppc_6xx\0" \
147 "u-boot=muas3001/u-boot.bin\0" \
148 "bootfile=muas3001/uImage\0" \
149 "fdt_file=muas3001/muas3001.dtb\0" \
150 "ramdisk_file=uRamdisk\0" \
151 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
152 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
153 "cp.b ${u-boot_addr_r} ff000000 ${filesize};" \
154 "prot on ff000000 ff03ffff\0" \
155 "ramargs=setenv bootargs root=/dev/ram rw\0" \
156 "nfsargs=setenv bootargs root=/dev/nfs rw " \
157 "nfsroot=${serverip}:${rootpath}\0" \
158 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
159 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
160 "addip=setenv bootargs ${bootargs} " \
161 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
162 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
163 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
164 "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \
165 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
166 "net_self=tftp ${kernel_addr_r} ${bootfile}; " \
167 "tftp ${fdt_addr_r} ${fdt_file}; " \
168 "tftp ${ramdisk_addr} ${ramdisk_file}; " \
169 "run ramargs addip; " \
170 "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \
171 "ramdisk_addr=ff210000\0" \
172 "kernel_addr=ff050000\0" \
173 "fdt_addr=ff200000\0" \
174 "flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \
175 " ${ramdisk_addr} ${fdt_addr}\0" \
176 "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \
177 " ${ramdisk_file};" \
178 "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \
179 "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \
181 "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \
182 "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \
183 "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \
186 #define CONFIG_BOOTCOMMAND "run net_nfs"
187 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
190 * Miscellaneous configurable options
192 #define CONFIG_SYS_HUSH_PARSER
193 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
194 #define CONFIG_SYS_LONGHELP /* undef to save memory */
195 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
196 #if defined(CONFIG_CMD_KGDB)
197 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
199 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
201 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
202 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
203 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
205 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
206 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
208 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
210 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
212 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
214 #define CONFIG_SYS_SDRAM_BASE 0x00000000
215 #define CONFIG_SYS_FLASH_BASE 0xFF000000
216 #define CONFIG_SYS_FLASH_SIZE 32
217 #define CONFIG_SYS_FLASH_CFI
218 #define CONFIG_FLASH_CFI_DRIVER
219 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
220 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
222 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
224 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
225 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
226 #define CONFIG_SYS_RAMBOOT
229 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
231 #define CONFIG_ENV_IS_IN_FLASH
233 #ifdef CONFIG_ENV_IS_IN_FLASH
234 #define CONFIG_ENV_SECT_SIZE 0x10000
235 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
236 #endif /* CONFIG_ENV_IS_IN_FLASH */
241 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
242 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
243 #define CONFIG_SYS_I2C_SLAVE 0x7F
245 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
246 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
247 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
248 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
249 #define CONFIG_SYS_DTT_MAX_TEMP 70
250 #define CONFIG_SYS_DTT_LOW_TEMP -30
251 #define CONFIG_SYS_DTT_HYSTERESIS 3
253 #define CONFIG_SYS_IMMR 0xF0000000
254 #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
256 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
257 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
258 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
259 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
260 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
262 /* Hard reset configuration word */
263 #define CONFIG_SYS_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */
266 #define CONFIG_SYS_HRCW_SLAVE1 0
267 #define CONFIG_SYS_HRCW_SLAVE2 0
268 #define CONFIG_SYS_HRCW_SLAVE3 0
269 #define CONFIG_SYS_HRCW_SLAVE4 0
270 #define CONFIG_SYS_HRCW_SLAVE5 0
271 #define CONFIG_SYS_HRCW_SLAVE6 0
272 #define CONFIG_SYS_HRCW_SLAVE7 0
274 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
275 #define BOOTFLAG_WARM 0x02 /* Software reboot */
277 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
278 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
280 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
281 #if defined(CONFIG_CMD_KGDB)
282 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
285 #define CONFIG_SYS_HID0_INIT 0
286 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
288 #define CONFIG_SYS_HID2 0
290 #define CONFIG_SYS_SIUMCR 0x00200000
291 #define CONFIG_SYS_BCR 0x004c0000
292 #define CONFIG_SYS_SCCR 0x0
294 /*-----------------------------------------------------------------------
295 * SYPCR - System Protection Control 4-35
296 * SYPCR can only be written once after reset!
297 *-----------------------------------------------------------------------
298 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
300 #if defined(CONFIG_WATCHDOG)
301 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
302 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
304 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
305 SYPCR_SWRI|SYPCR_SWP)
306 #endif /* CONFIG_WATCHDOG */
308 /*-----------------------------------------------------------------------
309 * RMR - Reset Mode Register 5-5
310 *-----------------------------------------------------------------------
311 * turn on Checkstop Reset Enable
313 #define CONFIG_SYS_RMR 0
315 /*-----------------------------------------------------------------------
316 * TMCNTSC - Time Counter Status and Control 4-40
317 *-----------------------------------------------------------------------
318 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
319 * and enable Time Counter
321 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
323 /*-----------------------------------------------------------------------
324 * PISCR - Periodic Interrupt Status and Control 4-42
325 *-----------------------------------------------------------------------
326 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
329 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
331 /*-----------------------------------------------------------------------
332 * RCCR - RISC Controller Configuration 13-7
333 *-----------------------------------------------------------------------
335 #define CONFIG_SYS_RCCR 0
338 * Init Memory Controller:
340 * Bank Bus Machine PortSz Device
341 * ---- --- ------- ------ ------
342 * 0 60x GPCM 32 bit FLASH
343 * 1 60x SDRAM 64 bit SDRAM
344 * 4 60x GPCM 16 bit I/O Ctrl
349 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
354 #define CONFIG_SYS_OR0_PRELIM (0xff000020)
356 /* Bank 1 - 60x bus SDRAM
358 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
360 #define CONFIG_SYS_MPTPR 0x2800
362 /*-----------------------------------------------------------------------------
363 * Address for Mode Register Set (MRS) command
364 *-----------------------------------------------------------------------------
366 #define CONFIG_SYS_MRS_OFFS 0x00000110
367 #define CONFIG_SYS_PSRT 0x13
369 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
374 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_LITTLE
376 /* SDRAM initialization values
378 #define CONFIG_SYS_OR1_LITTLE ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
380 ORxS_ROWST_PBI1_A7 |\
383 #define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3
385 #define CONFIG_SYS_OR1_BIG ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
387 ORxS_ROWST_PBI1_A4 |\
390 #define CONFIG_SYS_PSDMR_BIG 0x014f36a3
392 /* IO on CS4 initialization values
394 #define CONFIG_SYS_IO_BASE 0xc0000000
395 #define CONFIG_SYS_IO_SIZE 1
397 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
398 BRx_PS_16 | BRx_MS_GPCM_L | BRx_V)
400 #define CONFIG_SYS_OR4_PRELIM (0xfff80020)
402 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
404 /* pass open firmware flat tree */
405 #define CONFIG_OF_LIBFDT 1
406 #define CONFIG_OF_BOARD_SETUP 1
408 #define OF_CPU "PowerPC,8270@0"
409 #define OF_SOC "soc@f0000000"
410 #define OF_TBCLK (bd->bi_busfreq / 4)
411 #if defined(CONFIG_MUAS_DEV_BOARD)
412 #define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
414 #define OF_STDOUT_PATH "/soc/cpm/serial@11a80"
417 #endif /* __CONFIG_H */