sunxi: Add support for using MII phy-s with the GMAC nic
[oweals/u-boot.git] / include / configs / muas3001.h
1 /*
2  * (C) Copyright 2008
3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #ifndef __CONFIG_H
9 #define __CONFIG_H
10
11 /*
12  * High Level Configuration Options
13  * (easy to change)
14  */
15
16 #define CONFIG_MUAS3001         1
17
18 #define CONFIG_SYS_TEXT_BASE    0xFF000000
19
20 #define CONFIG_CPM2             1       /* Has a CPM2 */
21
22 /* Do boardspecific init */
23 #define CONFIG_BOARD_EARLY_INIT_R       1
24
25 /* enable Watchdog */
26 #define CONFIG_WATCHDOG         1
27
28 /*
29  * Select serial console configuration
30  *
31  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
32  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
33  * for SCC).
34  */
35 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
36 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
37 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
38 #if defined(CONFIG_MUAS_DEV_BOARD)
39 #define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
40 #else
41 #define CONFIG_CONS_INDEX       1       /* SMC1 is used for console  */
42 #endif
43
44 /*
45  * Select ethernet configuration
46  *
47  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
48  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
49  * SCC, 1-3 for FCC)
50  *
51  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
52  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
53  * must be unset.
54  */
55 #undef  CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
56 #define CONFIG_ETHER_ON_FCC             /* Ethernet is on FCC     */
57 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
58
59 #define CONFIG_ETHER_INDEX      1
60 #define CONFIG_ETHER_ON_FCC1
61 #define CONFIG_HAS_ETH0
62 #define FCC_ENET
63
64 /*
65  * - Rx-CLK is CLK11
66  * - Tx-CLK is CLK12
67  */
68 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
69 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
70 /*
71  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
72  */
73 # define CONFIG_SYS_CPMFCR_RAMTYPE      (0)
74 /* know on local Bus */
75 /* define CONFIG_SYS_CPMFCR_RAMTYPE     (CPMFCR_DTB | CPMFCR_BDB) */
76 /*
77  * - Enable Full Duplex in FSMR
78  */
79 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
80
81 #define CONFIG_MII                      /* MII PHY management           */
82 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
83 # define CONFIG_SYS_PHY_ADDR            1
84 /*
85  * GPIO pins used for bit-banged MII communications
86  */
87 #define MDIO_PORT       0               /* Port A */
88 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
89                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
90 #define MDC_DECLARE     MDIO_DECLARE
91
92
93 #define CONFIG_SYS_MDIO_PIN     0x00200000      /* PA10 */
94 #define CONFIG_SYS_MDC_PIN      0x00400000      /* PA9  */
95
96 #define MDIO_ACTIVE     (iop->pdir |=  CONFIG_SYS_MDIO_PIN)
97 #define MDIO_TRISTATE   (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
98 #define MDIO_READ       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
99
100 #define MDIO(bit)       if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
101                         else    iop->pdat &= ~CONFIG_SYS_MDIO_PIN
102
103 #define MDC(bit)        if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
104                         else    iop->pdat &= ~CONFIG_SYS_MDC_PIN
105
106 #define MIIDELAY        udelay(1)
107
108 #ifndef CONFIG_8260_CLKIN
109 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
110 #endif
111
112 #define CONFIG_BAUDRATE         115200
113
114 /*
115  * Command line configuration.
116  */
117 #include <config_cmd_default.h>
118
119 #define CONFIG_CMD_DTT
120 #define CONFIG_CMD_ECHO
121 #define CONFIG_CMD_IMMAP
122 #define CONFIG_CMD_MII
123 #define CONFIG_CMD_PING
124 #define CONFIG_CMD_I2C
125
126 /*
127  * Default environment settings
128  */
129 #define CONFIG_EXTRA_ENV_SETTINGS                                               \
130         "netdev=eth0\0"                                                         \
131         "u-boot_addr_r=100000\0"                                                \
132         "kernel_addr_r=200000\0"                                                \
133         "fdt_addr_r=400000\0"                                                   \
134         "rootpath=/opt/eldk/ppc_6xx\0"                                          \
135         "u-boot=muas3001/u-boot.bin\0"                                          \
136         "bootfile=muas3001/uImage\0"                                            \
137         "fdt_file=muas3001/muas3001.dtb\0"                                      \
138         "ramdisk_file=uRamdisk\0"                                               \
139         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                                \
140         "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "            \
141                 "cp.b ${u-boot_addr_r} ff000000 ${filesize};"                   \
142                 "prot on ff000000 ff03ffff\0"                                   \
143         "ramargs=setenv bootargs root=/dev/ram rw\0"                            \
144         "nfsargs=setenv bootargs root=/dev/nfs rw "                             \
145                 "nfsroot=${serverip}:${rootpath}\0"                             \
146         "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0"     \
147         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"                      \
148         "addip=setenv bootargs ${bootargs} "                                    \
149                 "ip=${ipaddr}:${serverip}:${gatewayip}:"                        \
150                 "${netmask}:${hostname}:${netdev}:off panic=1\0"                \
151         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                           \
152                 "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;"    \
153                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"                      \
154         "net_self=tftp ${kernel_addr_r} ${bootfile}; "                          \
155                 "tftp ${fdt_addr_r} ${fdt_file}; "                              \
156                 "tftp ${ramdisk_addr} ${ramdisk_file}; "                        \
157                 "run ramargs addip; "                                           \
158                 "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0"        \
159         "ramdisk_addr=ff210000\0"                                               \
160         "kernel_addr=ff050000\0"                                                \
161         "fdt_addr=ff200000\0"                                                   \
162         "flash_self=run ramargs addip addcons;bootm ${kernel_addr}"             \
163         " ${ramdisk_addr} ${fdt_addr}\0"                                        \
164         "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}"      \
165         " ${ramdisk_file};"                                                     \
166         "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0"                   \
167         "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}"        \
168         " ${bootfile};"                                                         \
169         "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0"                    \
170         "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};"     \
171         "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0"                          \
172         ""
173
174 #define CONFIG_BOOTCOMMAND      "run net_nfs"
175 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
176
177 /*
178  * Miscellaneous configurable options
179  */
180 #define CONFIG_SYS_HUSH_PARSER
181 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
182 #if defined(CONFIG_CMD_KGDB)
183 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
184 #else
185 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
186 #endif
187 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size  */
188 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
189 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size  */
190
191 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
192 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
193
194 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
195
196 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
197
198 #define CONFIG_SYS_SDRAM_BASE           0x00000000
199 #define CONFIG_SYS_FLASH_BASE           0xFF000000
200 #define CONFIG_SYS_FLASH_SIZE           32
201 #define CONFIG_SYS_FLASH_CFI
202 #define CONFIG_FLASH_CFI_DRIVER
203 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks       */
204 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
205
206 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
207
208 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
209 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
210 #define CONFIG_SYS_RAMBOOT
211 #endif
212
213 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256KB for Monitor */
214
215 #define CONFIG_ENV_IS_IN_FLASH
216
217 #ifdef CONFIG_ENV_IS_IN_FLASH
218 #define CONFIG_ENV_SECT_SIZE    0x10000
219 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
220 #endif /* CONFIG_ENV_IS_IN_FLASH */
221
222 /*
223  * I2C Bus
224  */
225 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
226 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
227 #define CONFIG_SYS_I2C_SLAVE            0x7F
228
229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
230 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
231 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
232 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
233 #define CONFIG_SYS_DTT_MAX_TEMP 70
234 #define CONFIG_SYS_DTT_LOW_TEMP -30
235 #define CONFIG_SYS_DTT_HYSTERESIS       3
236
237 #define CONFIG_SYS_IMMR         0xF0000000
238 #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
239
240 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
241 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in DPRAM   */
242 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
243 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
244
245 /* Hard reset configuration word */
246 #define CONFIG_SYS_HRCW_MASTER          0x0E028200      /* BPS=11 CIP=1 ISB=010 BMS=1 */
247
248 /* No slaves */
249 #define CONFIG_SYS_HRCW_SLAVE1  0
250 #define CONFIG_SYS_HRCW_SLAVE2  0
251 #define CONFIG_SYS_HRCW_SLAVE3  0
252 #define CONFIG_SYS_HRCW_SLAVE4  0
253 #define CONFIG_SYS_HRCW_SLAVE5  0
254 #define CONFIG_SYS_HRCW_SLAVE6  0
255 #define CONFIG_SYS_HRCW_SLAVE7  0
256
257 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
258 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
259
260 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
261 #if defined(CONFIG_CMD_KGDB)
262 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
263 #endif
264
265 #define CONFIG_SYS_HID0_INIT            0
266 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
267
268 #define CONFIG_SYS_HID2         0
269
270 #define CONFIG_SYS_SIUMCR               0x00200000
271 #define CONFIG_SYS_BCR                  0x004c0000
272 #define CONFIG_SYS_SCCR         0x0
273
274 /*-----------------------------------------------------------------------
275  * SYPCR - System Protection Control                             4-35
276  * SYPCR can only be written once after reset!
277  *-----------------------------------------------------------------------
278  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
279  */
280 #if defined(CONFIG_WATCHDOG)
281 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
282                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
283 #else
284 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
285                          SYPCR_SWRI|SYPCR_SWP)
286 #endif /* CONFIG_WATCHDOG */
287
288 /*-----------------------------------------------------------------------
289  * RMR - Reset Mode Register                                     5-5
290  *-----------------------------------------------------------------------
291  * turn on Checkstop Reset Enable
292  */
293 #define CONFIG_SYS_RMR         0
294
295 /*-----------------------------------------------------------------------
296  * TMCNTSC - Time Counter Status and Control                     4-40
297  *-----------------------------------------------------------------------
298  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
299  * and enable Time Counter
300  */
301 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
302
303 /*-----------------------------------------------------------------------
304  * PISCR - Periodic Interrupt Status and Control                 4-42
305  *-----------------------------------------------------------------------
306  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
307  * Periodic timer
308  */
309 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
310
311 /*-----------------------------------------------------------------------
312  * RCCR - RISC Controller Configuration                         13-7
313  *-----------------------------------------------------------------------
314  */
315 #define CONFIG_SYS_RCCR        0
316
317 /*
318  * Init Memory Controller:
319  *
320  * Bank Bus     Machine PortSz  Device
321  * ---- ---     ------- ------  ------
322  *  0   60x     GPCM    32 bit  FLASH
323  *  1   60x     SDRAM   64 bit  SDRAM
324  *  4   60x     GPCM    16 bit  I/O Ctrl
325  *
326  */
327 /* Bank 0 - FLASH
328  */
329 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)    |\
330                          BRx_PS_32                      |\
331                          BRx_MS_GPCM_P                  |\
332                          BRx_V)
333
334 #define CONFIG_SYS_OR0_PRELIM (0xff000020)
335
336 /* Bank 1 - 60x bus SDRAM
337  */
338 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (256 << 20)     /* less than 256 MB */
339
340 #define CONFIG_SYS_MPTPR       0x2800
341
342 /*-----------------------------------------------------------------------------
343  * Address for Mode Register Set (MRS) command
344  *-----------------------------------------------------------------------------
345  */
346 #define CONFIG_SYS_MRS_OFFS     0x00000110
347 #define CONFIG_SYS_PSRT        0x13
348
349 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
350                          BRx_PS_64                      |\
351                          BRx_MS_SDRAM_P                 |\
352                          BRx_V)
353
354 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1_LITTLE
355
356 /* SDRAM initialization values
357 */
358 #define CONFIG_SYS_OR1_LITTLE   ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
359                          ORxS_BPD_4                     |\
360                          ORxS_ROWST_PBI1_A7             |\
361                          ORxS_NUMR_12)
362
363 #define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3
364
365 #define CONFIG_SYS_OR1_BIG      ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
366                          ORxS_BPD_4                     |\
367                          ORxS_ROWST_PBI1_A4             |\
368                          ORxS_NUMR_12)
369
370 #define CONFIG_SYS_PSDMR_BIG            0x014f36a3
371
372 /* IO on CS4 initialization values
373 */
374 #define CONFIG_SYS_IO_BASE      0xc0000000
375 #define CONFIG_SYS_IO_SIZE      1
376
377 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
378                          BRx_PS_16 | BRx_MS_GPCM_L | BRx_V)
379
380 #define CONFIG_SYS_OR4_PRELIM   (0xfff80020)
381
382 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address                */
383
384 /* pass open firmware flat tree */
385 #define CONFIG_OF_LIBFDT        1
386 #define CONFIG_OF_BOARD_SETUP   1
387
388 #define OF_TBCLK                (bd->bi_busfreq / 4)
389 #if defined(CONFIG_MUAS_DEV_BOARD)
390 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
391 #else
392 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a80"
393 #endif
394
395 #endif /* __CONFIG_H */