1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
24 #define CONFIG_SYS_GPIO1_PRELIM
25 /* GPIO Default input/output settings */
26 #define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00
28 * Default GPIO values:
29 * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
31 #define CONFIG_SYS_GPIO1_DAT 0x08008C00
36 #define CONFIG_FSL_SERDES
37 #define CONFIG_FSL_SERDES1 0xe3000
39 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
44 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
46 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
47 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
48 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
55 * Manually set up DDR parameters
56 * consist of two chips HY5PS12621BFP-C4 from HYNIX
59 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
61 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
62 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
63 | CSCONFIG_ODT_RD_NEVER \
64 | CSCONFIG_ODT_WR_ONLY_CURRENT \
65 | CSCONFIG_ROW_BIT_13 \
66 | CSCONFIG_COL_BIT_10)
68 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
69 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
70 | (0 << TIMING_CFG0_WRT_SHIFT) \
71 | (0 << TIMING_CFG0_RRT_SHIFT) \
72 | (0 << TIMING_CFG0_WWT_SHIFT) \
73 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
74 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
75 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
76 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
78 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
79 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
80 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
81 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
82 | (6 << TIMING_CFG1_REFREC_SHIFT) \
83 | (2 << TIMING_CFG1_WRREC_SHIFT) \
84 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
85 | (2 << TIMING_CFG1_WRTORD_SHIFT))
87 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
88 | (4 << TIMING_CFG2_CPO_SHIFT) \
89 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
90 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
91 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
92 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
93 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
95 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
96 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
98 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
99 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
103 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
104 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
105 | (0x0232 << SDRAM_MODE_SD_SHIFT))
106 /* ODT 150ohm CL=3, AL=1 on SDRAM */
107 #define CONFIG_SYS_DDR_MODE2 0x00000000
112 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
113 #define CONFIG_SYS_MEMTEST_END 0x07f00000
116 * The reserved memory
118 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
120 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
121 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
124 * Initial RAM Base Address Setup
126 #define CONFIG_SYS_INIT_RAM_LOCK 1
127 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
128 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
129 #define CONFIG_SYS_GBL_DATA_OFFSET \
130 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
133 * Local Bus Configuration & Clock Setup
135 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
136 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
137 #define CONFIG_SYS_LBC_LBCR 0x00040000
140 * FLASH on the Local Bus
142 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
144 #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */
145 #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
148 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
149 #define CONFIG_SYS_MAX_FLASH_SECT 512
151 /* Flash Erase Timeout (ms) */
152 #define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024)
153 /* Flash Write Timeout (ms) */
154 #define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024)
157 * SJA1000 CAN controller on Local Bus
159 #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
165 #define CONFIG_SYS_CPLD_BASE 0xFBFF8000
171 #undef CONFIG_SERIAL_SOFTWARE_FIFO
172 #define CONFIG_SYS_NS16550_SERIAL
173 #define CONFIG_SYS_NS16550_REG_SIZE 1
174 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
176 #define CONFIG_SYS_BAUDRATE_TABLE \
177 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
179 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
180 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
183 #define CONFIG_SYS_I2C
184 #define CONFIG_SYS_I2C_FSL
185 #define CONFIG_SYS_FSL_I2C_SPEED 400000
186 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
187 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
188 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
189 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
190 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
194 * Addresses are mapped 1-1.
196 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
197 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
198 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
199 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
200 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
201 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
202 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
203 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
204 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
206 /* enable PCIE clock */
207 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
209 #define CONFIG_PCI_INDIRECT_BRIDGE
212 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
213 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
218 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
219 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
220 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
221 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
224 * TSEC ethernet configuration
226 #define CONFIG_TSEC1_NAME "eTSEC0"
227 #define CONFIG_TSEC2_NAME "eTSEC1"
228 #define TSEC1_PHY_ADDR 1
229 #define TSEC2_PHY_ADDR 2
230 #define TSEC1_PHYIDX 0
231 #define TSEC2_PHYIDX 0
232 #define TSEC1_FLAGS 0
233 #define TSEC2_FLAGS 0
235 /* Options are: eTSEC[0-1] */
236 #define CONFIG_ETHPRIME "eTSEC0"
241 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
242 CONFIG_SYS_MONITOR_LEN)
243 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
244 #define CONFIG_ENV_SIZE 0x2000
245 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
246 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
248 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
249 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
254 #define CONFIG_BOOTP_BOOTFILESIZE
257 * Command line configuration.
261 * Miscellaneous configurable options
263 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
265 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
267 /* Boot Argument Buffer Size */
268 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
271 * For booting Linux, the board info and command line data
272 * have to be in the first 8 MB of memory, since this is
273 * the maximum mapped by the Linux kernel during initialization.
275 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
278 * Environment Configuration
281 #define CONFIG_ENV_OVERWRITE
283 #if defined(CONFIG_TSEC_ENET)
284 #define CONFIG_HAS_ETH0
285 #define CONFIG_HAS_ETH1
288 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
291 #define CONFIG_EXTRA_ENV_SETTINGS \
293 "consoledev=ttyS0\0" \
294 "nfsargs=setenv bootargs root=/dev/nfs rw " \
295 "nfsroot=${serverip}:${rootpath}\0" \
296 "ramargs=setenv bootargs root=/dev/ram rw\0" \
297 "addip=setenv bootargs ${bootargs} " \
298 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
299 ":${hostname}:${netdev}:off panic=1\0" \
300 "addtty=setenv bootargs ${bootargs}" \
301 " console=${consoledev},${baudrate}\0" \
302 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
303 "addmisc=setenv bootargs ${bootargs}\0" \
304 "kernel_addr=FC0A0000\0" \
305 "fdt_addr=FC2A0000\0" \
306 "ramdisk_addr=FC2C0000\0" \
307 "u-boot=mpc8308_p1m/u-boot.bin\0" \
308 "kernel_addr_r=1000000\0" \
309 "fdt_addr_r=C00000\0" \
310 "hostname=mpc8308_p1m\0" \
311 "bootfile=mpc8308_p1m/uImage\0" \
312 "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \
313 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
314 "flash_self=run ramargs addip addtty addmtd addmisc;" \
315 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
316 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
317 "bootm ${kernel_addr} - ${fdt_addr}\0" \
318 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
319 "tftp ${fdt_addr_r} ${fdtfile};" \
320 "run nfsargs addip addtty addmtd addmisc;" \
321 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
322 "bootcmd=run flash_self\0" \
323 "load=tftp ${loadaddr} ${u-boot}\0" \
324 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
325 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
326 " +${filesize};cp.b ${fileaddr} " \
327 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
328 "upd=run load update\0" \
330 #endif /* __CONFIG_H */