sunxi: Add support for using MII phy-s with the GMAC nic
[oweals/u-boot.git] / include / configs / mpc5121ads.h
1 /*
2  * (C) Copyright 2007-2009 DENX Software Engineering
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * MPC5121ADS board configuration file
9  */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #define CONFIG_MPC5121ADS 1
15 /*
16  * Memory map for the MPC5121ADS board:
17  *
18  * 0x0000_0000 - 0x0FFF_FFFF    DDR RAM (256 MB)
19  * 0x3000_0000 - 0x3001_FFFF    SRAM (128 KB)
20  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
21  * 0x8200_0000 - 0x8200_001F    CPLD (32 B)
22  * 0x8400_0000 - 0x82FF_FFFF    PCI I/O space (16 MB)
23  * 0xA000_0000 - 0xAFFF_FFFF    PCI memory space (256 MB)
24  * 0xB000_0000 - 0xBFFF_FFFF    PCI memory mapped I/O space (256 MB)
25  * 0xFC00_0000 - 0xFFFF_FFFF    NOR Boot FLASH (64 MB)
26  */
27
28 /*
29  * High Level Configuration Options
30  */
31 #define CONFIG_E300             1       /* E300 Family */
32
33 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
34
35 /* video */
36 #ifdef CONFIG_FSL_DIU_FB
37 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_IMMR + 0x2100)
38 #define CONFIG_VIDEO
39 #define CONFIG_CMD_BMP
40 #define CONFIG_CFB_CONSOLE
41 #define CONFIG_VIDEO_SW_CURSOR
42 #define CONFIG_VGA_AS_SINGLE_DEVICE
43 #define CONFIG_VIDEO_LOGO
44 #define CONFIG_VIDEO_BMP_LOGO
45 #endif
46
47 /* CONFIG_PCI is defined at config time */
48
49 #ifdef CONFIG_MPC5121ADS_REV2
50 #define CONFIG_SYS_MPC512X_CLKIN        66000000        /* in Hz */
51 #else
52 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
53 #define CONFIG_PCI
54 #endif
55
56 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f() */
57 #define CONFIG_MISC_INIT_R
58
59 #define CONFIG_SYS_IMMR         0x80000000
60
61 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
62 #define CONFIG_SYS_MEMTEST_END          0x00400000
63
64 /*
65  * DDR Setup - manually set all parameters as there's no SPD etc.
66  */
67 #ifdef CONFIG_MPC5121ADS_REV2
68 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
69 #else
70 #define CONFIG_SYS_DDR_SIZE             512             /* MB */
71 #endif
72 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
73 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
74 #define CONFIG_SYS_MAX_RAM_SIZE         0x20000000
75
76 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000036
77
78 /* DDR Controller Configuration
79  *
80  * SYS_CFG:
81  *      [31:31] MDDRC Soft Reset:       Diabled
82  *      [30:30] DRAM CKE pin:           Enabled
83  *      [29:29] DRAM CLK:               Enabled
84  *      [28:28] Command Mode:           Enabled (For initialization only)
85  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
86  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
87  *      [20:19] Read Test:              DON'T USE
88  *      [18:18] Self Refresh:           Enabled
89  *      [17:17] 16bit Mode:             Disabled
90  *      [16:13] Ready Delay:            2
91  *      [12:12] Half DQS Delay:         Disabled
92  *      [11:11] Quarter DQS Delay:      Disabled
93  *      [10:08] Write Delay:            2
94  *      [07:07] Early ODT:              Disabled
95  *      [06:06] On DIE Termination:     Disabled
96  *      [05:05] FIFO Overflow Clear:    DON'T USE here
97  *      [04:04] FIFO Underflow Clear:   DON'T USE here
98  *      [03:03] FIFO Overflow Pending:  DON'T USE here
99  *      [02:02] FIFO Underlfow Pending: DON'T USE here
100  *      [01:01] FIFO Overlfow Enabled:  Enabled
101  *      [00:00] FIFO Underflow Enabled: Enabled
102  * TIME_CFG0
103  *      [31:16] DRAM Refresh Time:      0 CSB clocks
104  *      [15:8]  DRAM Command Time:      0 CSB clocks
105  *      [07:00] DRAM Precharge Time:    0 CSB clocks
106  * TIME_CFG1
107  *      [31:26] DRAM tRFC:
108  *      [25:21] DRAM tWR1:
109  *      [20:17] DRAM tWRT1:
110  *      [16:11] DRAM tDRR:
111  *      [10:05] DRAM tRC:
112  *      [04:00] DRAM tRAS:
113  * TIME_CFG2
114  *      [31:28] DRAM tRCD:
115  *      [27:23] DRAM tFAW:
116  *      [22:19] DRAM tRTW1:
117  *      [18:15] DRAM tCCD:
118  *      [14:10] DRAM tRTP:
119  *      [09:05] DRAM tRP:
120  *      [04:00] DRAM tRPA
121  */
122 #ifdef CONFIG_MPC5121ADS_REV2
123 #define CONFIG_SYS_MDDRC_SYS_CFG        0xE8604A00
124 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x54EC1168
125 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x35210864
126 #else
127 #define CONFIG_SYS_MDDRC_SYS_CFG        0xEA804A00
128 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x68EC1168
129 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34310864
130 #endif
131 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x06183D2E
132
133 #define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA         0xEA802B00
134 #define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA       0x690e1189
135 #define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA       0x35310864
136
137 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
138 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
139 #define CONFIG_SYS_DDRCMD_EM2           0x01020000
140 #define CONFIG_SYS_DDRCMD_EM3           0x01030000
141 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010000
142 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
143
144 #define DDRCMD_EMR_OCD(pr, ohm) ( \
145         (1 << 24)          | /* MDDRC Command Request   */ \
146         (1 << 16)          | /* MODE Reg BA[2:0]        */ \
147         (0 << 12)          | /* Outputs 0=Enabled       */ \
148         (0 << 11)          | /* RDQS                    */ \
149         (1 << 10)          | /* DQS#                    */ \
150         (pr <<  7)         | /* OCD prog 7=deflt,0=exit */ \
151                     /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
152         ((ohm & 0x2) <<  5)| /* Rtt1                    */ \
153         (0 <<  3)          | /* additive posted CAS#    */ \
154         ((ohm & 0x1) <<  2)| /* Rtt0                    */ \
155         (0 <<  0)          | /* Output Drive Strength   */ \
156         (0 <<  0))           /* DLL Enable 0=Normal     */
157
158 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   DDRCMD_EMR_OCD(7, 0)
159 #define CONFIG_SYS_ELPIDA_OCD_EXIT      DDRCMD_EMR_OCD(0, 0)
160
161 #define DDRCMD_MODE_REG(cas, wr) ( \
162         (1 << 24)    | /* MDDRC Command Request                 */ \
163         (0 << 16)    | /* MODE Reg BA[2:0]                      */ \
164         ((wr-1) << 9)| /* Write Recovery                        */ \
165         (cas << 4)   | /* CAS                                   */ \
166         (0 << 3)     | /* Burst Type:0=Sequential,1=Interleaved */ \
167         (2 << 0))      /* 4 or 8 Burst Length:0x2=4 0x3=8       */
168
169 #define CONFIG_SYS_MICRON_INIT_DEV_OP   DDRCMD_MODE_REG(3, 3)
170 #define CONFIG_SYS_ELPIDA_INIT_DEV_OP   DDRCMD_MODE_REG(4, 4)
171 #define CONFIG_SYS_ELPIDA_RES_DLL       (DDRCMD_MODE_REG(4, 4) | (1 << 8))
172
173 /* DDR Priority Manager Configuration */
174 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
175 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
176 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
177 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
178 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
179 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
180 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
181 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
182 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
183 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
184 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
185 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
186 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
187 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
188 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
189 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
190 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
191 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
192 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
193 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
194 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
195 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
196 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
197
198 /*
199  * NOR FLASH on the Local Bus
200  */
201 #undef CONFIG_BKUP_FLASH
202 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
203 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
204 #ifdef CONFIG_BKUP_FLASH
205 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
206 #define CONFIG_SYS_FLASH_SIZE           0x00800000      /* max flash size in bytes */
207 #else
208 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* start of FLASH   */
209 #define CONFIG_SYS_FLASH_SIZE           0x04000000      /* max flash size in bytes */
210 #endif
211 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
212 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
213 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
214 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max sectors per device */
215
216 #undef CONFIG_SYS_FLASH_CHECKSUM
217
218 /*
219  * NAND FLASH
220  * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
221  */
222 #define CONFIG_CMD_NAND                                 /* enable NAND support */
223 #define CONFIG_JFFS2_NAND                               /* with JFFS2 on it */
224 #define CONFIG_NAND_MPC5121_NFC
225 #define CONFIG_SYS_NAND_BASE            0x40000000
226
227 #define CONFIG_SYS_MAX_NAND_DEVICE      2
228 #define CONFIG_SYS_NAND_SELECT_DEVICE   /* driver supports mutipl. chips */
229
230 /*
231  * Configuration parameters for MPC5121 NAND driver
232  */
233 #define CONFIG_FSL_NFC_WIDTH 1
234 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
235 #define CONFIG_FSL_NFC_SPARE_SIZE 64
236 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
237
238 /*
239  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
240  * window is 64KB
241  */
242 #define CONFIG_SYS_CPLD_BASE            0x82000000
243 #define CONFIG_SYS_CPLD_SIZE            0x00010000      /* 64 KB */
244 #define CONFIG_SYS_CS2_START            CONFIG_SYS_CPLD_BASE
245 #define CONFIG_SYS_CS2_SIZE             CONFIG_SYS_CPLD_SIZE
246
247 #define CONFIG_SYS_SRAM_BASE            0x30000000
248 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
249
250 #define CONFIG_SYS_CS0_CFG              0x05059310      /* ALE active low, data size 4bytes */
251 #define CONFIG_SYS_CS2_CFG              0x05059010      /* ALE active low, data size 1byte */
252 #define CONFIG_SYS_CS_ALETIMING 0x00000005      /* Use alternative CS timing for CS0 and CS2 */
253
254 /* Use SRAM for initial stack */
255 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE            /* Initial RAM address */
256 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_SRAM_SIZE            /* Size of used area in RAM */
257
258 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
259 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
260
261 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE            /* Start of monitor */
262 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)            /* Reserve 512 kB for Mon */
263 #ifdef  CONFIG_FSL_DIU_FB
264 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)       /* Reserved for malloc */
265 #else
266 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
267 #endif
268
269 /*
270  * Serial Port
271  */
272 #define CONFIG_CONS_INDEX     1
273
274 /*
275  * Serial console configuration
276  */
277 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
278 #define CONFIG_SYS_PSC3
279 #if CONFIG_PSC_CONSOLE != 3
280 #error CONFIG_PSC_CONSOLE must be 3
281 #endif
282 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
283 #define CONFIG_SYS_BAUDRATE_TABLE  \
284         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
285
286 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC3_TX_SIZE
287 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC3_TX_ADDR
288 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC3_RX_SIZE
289 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC3_RX_ADDR
290
291 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
292 /* Use the HUSH parser */
293 #define CONFIG_SYS_HUSH_PARSER
294 #ifdef  CONFIG_SYS_HUSH_PARSER
295 #endif
296
297 /*
298  * Clocks in use
299  */
300 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
301                          CLOCK_SCCR1_DDR_EN |                           \
302                          CLOCK_SCCR1_FEC_EN |                           \
303                          CLOCK_SCCR1_LPC_EN |                           \
304                          CLOCK_SCCR1_NFC_EN |                           \
305                          CLOCK_SCCR1_PATA_EN |                          \
306                          CLOCK_SCCR1_PCI_EN |                           \
307                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
308                          CLOCK_SCCR1_PSCFIFO_EN |                       \
309                          CLOCK_SCCR1_TPR_EN)
310
311 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN |           \
312                          CLOCK_SCCR2_I2C_EN |           \
313                          CLOCK_SCCR2_MEM_EN |           \
314                          CLOCK_SCCR2_SPDIF_EN |         \
315                          CLOCK_SCCR2_USB1_EN |          \
316                          CLOCK_SCCR2_USB2_EN)
317
318 /*
319  * PCI
320  */
321 #ifdef CONFIG_PCI
322 #define CONFIG_PCI_INDIRECT_BRIDGE
323
324 /*
325  * General PCI
326  */
327 #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
328 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
329 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000      /* 256M */
330 #define CONFIG_SYS_PCI_MMIO_BASE        (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
331 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
332 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000      /* 256M */
333 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
334 #define CONFIG_SYS_PCI_IO_PHYS          0x84000000
335 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000      /* 16M */
336
337
338 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
339
340 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
341
342 #endif
343
344 /* I2C */
345 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
346 #define CONFIG_I2C_MULTI_BUS
347 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address */
348 #define CONFIG_SYS_I2C_SLAVE            0x7F
349 #if 0
350 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
351 #endif
352
353 /*
354  * IIM - IC Identification Module
355  */
356 #undef CONFIG_FSL_IIM
357
358 /*
359  * EEPROM configuration
360  */
361 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16-bit EEPROM address */
362 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* Atmel: AT24C32A-10TQ-2.7 */
363 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* 10ms of delay */
364 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32-Byte Page Write Mode */
365
366 /*
367  * Ethernet configuration
368  */
369 #define CONFIG_MPC512x_FEC      1
370 #define CONFIG_PHY_ADDR         0x1
371 #define CONFIG_MII              1       /* MII PHY management           */
372 #define CONFIG_FEC_AN_TIMEOUT   1
373 #define CONFIG_HAS_ETH0
374
375 /*
376  * Configure on-board RTC
377  */
378 #define CONFIG_RTC_M41T62                       /* use M41T62 rtc via i2 */
379 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68              */
380
381 /*
382  * USB  Support
383  */
384 #define CONFIG_CMD_USB
385
386 #if defined(CONFIG_CMD_USB)
387 #define CONFIG_USB_EHCI                         /* Enable EHCI Support  */
388 #define CONFIG_USB_EHCI_FSL                     /* On a FSL platform    */
389 #define CONFIG_EHCI_MMIO_BIG_ENDIAN             /* With big-endian regs */
390 #define CONFIG_EHCI_DESC_BIG_ENDIAN
391 #define CONFIG_EHCI_IS_TDI
392 #define CONFIG_USB_STORAGE
393 #endif
394
395 /*
396  * Environment
397  */
398 #define CONFIG_ENV_IS_IN_FLASH  1
399 /* This has to be a multiple of the Flash sector size */
400 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
401 #define CONFIG_ENV_SIZE         0x2000
402 #ifdef CONFIG_BKUP_FLASH
403 #define CONFIG_ENV_SECT_SIZE    0x20000 /* one sector (256K) for env */
404 #else
405 #define CONFIG_ENV_SECT_SIZE    0x40000 /* one sector (256K) for env */
406 #endif
407
408 /* Address and size of Redundant Environment Sector     */
409 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
410 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
411
412 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
413 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
414
415 #include <config_cmd_default.h>
416
417 #define CONFIG_CMD_ASKENV
418 #define CONFIG_CMD_DATE
419 #define CONFIG_CMD_DHCP
420 #define CONFIG_CMD_EEPROM
421 #define CONFIG_CMD_EXT2
422 #define CONFIG_CMD_I2C
423 #define CONFIG_CMD_IDE
424 #define CONFIG_CMD_JFFS2
425 #define CONFIG_CMD_MII
426 #define CONFIG_CMD_NFS
427 #define CONFIG_CMD_PING
428 #define CONFIG_CMD_REGINFO
429
430 #undef CONFIG_CMD_FUSE
431
432 #if defined(CONFIG_PCI)
433 #define CONFIG_CMD_PCI
434 #endif
435
436 /*
437  * Dynamic MTD partition support
438  */
439 #define CONFIG_CMD_MTDPARTS
440 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
441 #define CONFIG_FLASH_CFI_MTD
442 #define MTDIDS_DEFAULT          "nor0=fc000000.flash,nand0=mpc5121.nand"
443
444 /*
445  * NOR flash layout:
446  *
447  * FC000000 - FEABFFFF 42.75 MiB        User Data
448  * FEAC0000 - FFABFFFF  16 MiB          Root File System
449  * FFAC0000 - FFEBFFFF   4 MiB          Linux Kernel
450  * FFEC0000 - FFEFFFFF 256 KiB          Device Tree
451  * FFF00000 - FFFFFFFF   1 MiB          U-Boot (up to 512 KiB) and 2 x * env
452  *
453  * NAND flash layout: one big partition
454  */
455 #define MTDPARTS_DEFAULT        "mtdparts=fc000000.flash:43776k(user)," \
456                                                 "16m(rootfs),"          \
457                                                 "4m(kernel),"           \
458                                                 "256k(dtb),"            \
459                                                 "1m(u-boot);"           \
460                                         "mpc5121.nand:-(data)"
461
462
463 #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
464
465 #define CONFIG_DOS_PARTITION
466 #define CONFIG_MAC_PARTITION
467 #define CONFIG_ISO_PARTITION
468
469 #define CONFIG_CMD_FAT
470 #define CONFIG_SUPPORT_VFAT
471
472 #endif /* defined(CONFIG_CMD_IDE) */
473
474 /*
475  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
476  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
477  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
478  * to chapter 36 of the MPC5121e Reference Manual.
479  */
480 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
481 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
482
483  /*
484  * Miscellaneous configurable options
485  */
486 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
487 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
488
489 #ifdef CONFIG_CMD_KGDB
490         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
491 #else
492         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
493 #endif
494
495
496 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
497 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
498 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
499
500 /*
501  * For booting Linux, the board info and command line data
502  * have to be in the first 256 MB of memory, since this is
503  * the maximum mapped by the Linux kernel during initialization.
504  */
505 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
506
507 /* Cache Configuration */
508 #define CONFIG_SYS_DCACHE_SIZE          32768
509 #define CONFIG_SYS_CACHELINE_SIZE       32
510 #ifdef CONFIG_CMD_KGDB
511 #define CONFIG_SYS_CACHELINE_SHIFT      5       /*log base 2 of the above value*/
512 #endif
513
514 #define CONFIG_SYS_HID0_INIT    0x000000000
515 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
516 #define CONFIG_SYS_HID2 HID2_HBE
517
518 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
519
520 #ifdef CONFIG_CMD_KGDB
521 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
522 #endif
523
524 /*
525  * Environment Configuration
526  */
527 #define CONFIG_TIMESTAMP
528
529 #define CONFIG_HOSTNAME         mpc5121ads
530 #define CONFIG_BOOTFILE         "mpc5121ads/uImage"
531 #define CONFIG_ROOTPATH         "/opt/eldk/ppc_6xx"
532
533 #define CONFIG_LOADADDR         400000  /* default location for tftp and bootm */
534
535 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
536 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
537
538 #define CONFIG_BAUDRATE         115200
539
540 #define CONFIG_PREBOOT  "echo;" \
541         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
542         "echo"
543
544 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
545         "u-boot_addr_r=200000\0"                                        \
546         "kernel_addr_r=600000\0"                                        \
547         "fdt_addr_r=880000\0"                                           \
548         "ramdisk_addr_r=900000\0"                                       \
549         "u-boot_addr=FFF00000\0"                                        \
550         "kernel_addr=FFAC0000\0"                                        \
551         "fdt_addr=FFEC0000\0"                                           \
552         "ramdisk_addr=FEAC0000\0"                                       \
553         "ramdiskfile=mpc5121ads/uRamdisk\0"                             \
554         "u-boot=mpc5121ads/u-boot.bin\0"                                \
555         "bootfile=mpc5121ads/uImage\0"                                  \
556         "fdtfile=mpc5121ads/mpc5121ads.dtb\0"                           \
557         "rootpath=/opt/eldk/ppc_6xx\n"                                  \
558         "netdev=eth0\0"                                                 \
559         "consdev=ttyPSC0\0"                                             \
560         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
561                 "nfsroot=${serverip}:${rootpath}\0"                     \
562         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
563         "addip=setenv bootargs ${bootargs} "                            \
564                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
565                 ":${hostname}:${netdev}:off panic=1\0"                  \
566         "addtty=setenv bootargs ${bootargs} "                           \
567                 "console=${consdev},${baudrate}\0"                      \
568         "flash_nfs=run nfsargs addip addtty;"                           \
569                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
570         "flash_self=run ramargs addip addtty;"                          \
571                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
572         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
573                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
574                 "run nfsargs addip addtty;"                             \
575                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
576         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
577                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
578                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
579                 "run ramargs addip addtty;"                             \
580                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
581         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
582         "update=protect off ${u-boot_addr} +${filesize};"               \
583                 "era ${u-boot_addr} +${filesize};"                      \
584                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
585         "upd=run load update\0"                                         \
586         ""
587
588 #define CONFIG_BOOTCOMMAND      "run flash_self"
589
590 #define CONFIG_OF_LIBFDT        1
591 #define CONFIG_OF_BOARD_SETUP   1
592 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
593
594 #define OF_CPU                  "PowerPC,5121@0"
595 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
596 #define OF_TBCLK                (bd->bi_busfreq / 4)
597 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
598
599 /*-----------------------------------------------------------------------
600  * IDE/ATA stuff
601  *-----------------------------------------------------------------------
602  */
603
604 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
605 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
606 #undef  CONFIG_IDE_LED                  /* LED   for IDE not supported  */
607
608 #define CONFIG_IDE_RESET                /* reset for IDE supported      */
609 #define CONFIG_IDE_PREINIT
610
611 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
612 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
613
614 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
615 #define CONFIG_SYS_ATA_BASE_ADDR        get_pata_base()
616
617 /* Offset for data I/O                  RefMan MPC5121EE Table 28-10    */
618 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x00A0)
619
620 /* Offset for normal register accesses  */
621 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
622
623 /* Offset for alternate registers       RefMan MPC5121EE Table 28-23    */
624 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x00D8)
625
626 /* Interval between registers   */
627 #define CONFIG_SYS_ATA_STRIDE           4
628
629 #define ATA_BASE_ADDR                   get_pata_base()
630
631 /*
632  * Control register bit definitions
633  */
634 #define FSL_ATA_CTRL_FIFO_RST_B         0x80000000
635 #define FSL_ATA_CTRL_ATA_RST_B          0x40000000
636 #define FSL_ATA_CTRL_FIFO_TX_EN         0x20000000
637 #define FSL_ATA_CTRL_FIFO_RCV_EN        0x10000000
638 #define FSL_ATA_CTRL_DMA_PENDING        0x08000000
639 #define FSL_ATA_CTRL_DMA_ULTRA          0x04000000
640 #define FSL_ATA_CTRL_DMA_WRITE          0x02000000
641 #define FSL_ATA_CTRL_IORDY_EN           0x01000000
642
643 #endif  /* __CONFIG_H */