2 * (C) Copyright 2007-2008 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include "../board/xilinx/ml401/xparameters.h"
30 #define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
31 #define MICROBLAZE_V5 1
32 #define CONFIG_ML401 1 /* ML401 Board */
35 #ifdef XILINX_UARTLITE_BASEADDR
36 #define CONFIG_XILINX_UARTLITE
37 #define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
38 #define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
39 #define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
41 #ifdef XILINX_UART16550_BASEADDR
43 #define CFG_NS16550_SERIAL
44 #define CFG_NS16550_REG_SIZE 4
45 #define CONFIG_CONS_INDEX 1
46 #define CFG_NS16550_COM1 XILINX_UART16550_BASEADDR
47 #define CFG_NS16550_CLK XILINX_UART16550_CLOCK_HZ
48 #define CONFIG_BAUDRATE 115200
49 #define CFG_BAUDRATE_TABLE { 9600, 115200 }
53 /* setting reset address */
54 /*#define CFG_RESET_ADDRESS TEXT_BASE*/
57 #ifdef XILINX_EMAC_BASEADDR
58 #define CONFIG_XILINX_EMAC 1
60 #ifdef XILINX_EMACLITE_BASEADDR
61 #define CONFIG_XILINX_EMACLITE 1
67 #ifdef XILINX_GPIO_BASEADDR
69 #define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
72 /* interrupt controller */
74 #define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
75 #define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
79 #define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
80 #define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
81 #define FREQUENCE XILINX_CLOCK_FREQ
82 #define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
83 #define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
86 /* #define CFG_FSL_2 */
87 /* #define FSL_INTR_2 1 */
90 * memory layout - Example
91 * TEXT_BASE = 0x1200_0000;
92 * CFG_SRAM_BASE = 0x1000_0000;
93 * CFG_SRAM_SIZE = 0x0400_0000;
95 * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
96 * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
97 * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
99 * 0x1000_0000 CFG_SDRAM_BASE
101 * 0x1200_0000 TEXT_BASE
107 * 0x13F7_F000 CFG_MALLOC_BASE
108 * MALLOC_AREA 256kB Alloc
109 * 0x11FB_F000 CFG_MONITOR_BASE
110 * MONITOR_CODE 256kB Env
111 * 0x13FF_F000 CFG_GBL_DATA_OFFSET
112 * GLOBAL_DATA 4kB bd, gd
113 * 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
116 /* ddr sdram - main memory */
117 #define CFG_SDRAM_BASE XILINX_RAM_START
118 #define CFG_SDRAM_SIZE XILINX_RAM_SIZE
119 #define CFG_MEMTEST_START CFG_SDRAM_BASE
120 #define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000)
123 #define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
124 /* start of global data */
125 #define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
129 #define CFG_MONITOR_LEN SIZE
130 #define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
131 #define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
132 #define CFG_MALLOC_LEN SIZE
133 #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
136 #define CFG_INIT_SP_OFFSET CFG_MONITOR_BASE
142 #define CFG_FLASH_BASE XILINX_FLASH_START
143 #define CFG_FLASH_SIZE XILINX_FLASH_SIZE
144 #define CFG_FLASH_CFI 1
145 #define CFG_FLASH_CFI_DRIVER 1
146 #define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */
147 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
148 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
149 #define CFG_FLASH_PROTECTION /* hardware flash protection */
152 #define CFG_ENV_IS_NOWHERE 1
153 #define CFG_ENV_SIZE 0x1000
154 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
157 #define CFG_ENV_IS_IN_FLASH 1
158 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
159 #define CFG_ENV_ADDR (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE))
160 #define CFG_ENV_SIZE 0x40000
161 #endif /* !RAMBOOT */
164 #define CFG_NO_FLASH 1
165 #define CFG_ENV_IS_NOWHERE 1
166 #define CFG_ENV_SIZE 0x1000
167 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
168 #define CFG_FLASH_PROTECTION /* hardware flash protection */
172 #ifdef XILINX_SYSACE_BASEADDR
173 #define CONFIG_SYSTEMACE
174 /* #define DEBUG_SYSTEMACE */
175 #define SYSTEMACE_CONFIG_FPGA
176 #define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
177 #define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
178 #define CONFIG_DOS_PARTITION
184 #define CONFIG_BOOTP_BOOTFILESIZE
185 #define CONFIG_BOOTP_BOOTPATH
186 #define CONFIG_BOOTP_GATEWAY
187 #define CONFIG_BOOTP_HOSTNAME
190 * Command line configuration.
192 #include <config_cmd_default.h>
194 #define CONFIG_CMD_ASKENV
195 #define CONFIG_CMD_CACHE
196 #define CONFIG_CMD_IRQ
197 #define CONFIG_CMD_MFSL
198 #define CONFIG_CMD_PING
200 #if defined(CONFIG_SYSTEMACE)
201 #define CONFIG_CMD_EXT2
202 #define CONFIG_CMD_FAT
206 #define CONFIG_CMD_ECHO
207 #define CONFIG_CMD_FLASH
208 #define CONFIG_CMD_IMLS
209 #define CONFIG_CMD_JFFS2
212 #define CONFIG_CMD_ENV
213 #define CONFIG_CMD_SAVES
216 #undef CONFIG_CMD_FLASH
219 #if defined(CONFIG_CMD_JFFS2)
220 /* JFFS2 partitions */
221 #define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */
222 #define MTDIDS_DEFAULT "nor0=ml401-0"
224 /* default mtd partition table */
225 #define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\
226 "256k(env),3m(kernel),1m(romfs),"\
227 "1m(cramfs),-(jffs2)"
230 /* Miscellaneous configurable options */
231 #define CFG_PROMPT "U-Boot-mONStR> "
232 #define CFG_CBSIZE 512 /* size of console buffer */
233 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
234 #define CFG_MAXARGS 15 /* max number of command args */
236 #define CFG_LOAD_ADDR 0x12000000 /* default load address */
238 #define CONFIG_BOOTDELAY 30
239 #define CONFIG_BOOTARGS "root=romfs"
240 #define CONFIG_HOSTNAME "ml401"
241 #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
242 #define CONFIG_IPADDR 192.168.0.3
243 #define CONFIG_SERVERIP 192.168.0.5
244 #define CONFIG_GATEWAYIP 192.168.0.1
245 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
247 /* architecture dependent code */
248 #define CFG_USR_EXCEP /* user exception */
251 #define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo"
253 #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
255 "mtdparts=mtdparts=ml401-0:"\
256 "256k(u-boot),256k(env),3m(kernel),"\
257 "1m(romfs),1m(cramfs),-(jffs2)\0"
259 #define CONFIG_CMDLINE_EDITING
260 #define CONFIG_OF_LIBFDT 1
262 #endif /* __CONFIG_H */