2 * (C) Copyright 2007-2010 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include "../board/xilinx/microblaze-generic/xparameters.h"
15 #define MICROBLAZE_V5 1
17 /* linear and spi flash memory */
18 #ifdef XILINX_FLASH_START
21 #undef RAMENV /* hold environment in flash */
23 #ifdef XILINX_SPI_FLASH_BASEADDR
26 #undef RAMENV /* hold environment in flash */
30 #define RAMENV /* hold environment in RAM */
35 #ifdef XILINX_UARTLITE_BASEADDR
36 # define CONFIG_XILINX_UARTLITE
37 # define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
38 # define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
39 # define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
40 #elif XILINX_UART16550_BASEADDR
41 # define CONFIG_SYS_NS16550_SERIAL
42 # if defined(__MICROBLAZEEL__)
43 # define CONFIG_SYS_NS16550_REG_SIZE -4
45 # define CONFIG_SYS_NS16550_REG_SIZE 4
47 # define CONFIG_CONS_INDEX 1
48 # define CONFIG_SYS_NS16550_COM1 \
49 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
50 # define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
51 # define CONFIG_BAUDRATE 115200
53 /* The following table includes the supported baudrates */
54 # define CONFIG_SYS_BAUDRATE_TABLE \
55 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
57 # error Undefined uart
60 /* setting reset address */
61 /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
64 #undef CONFIG_SYS_ENET
65 #if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL)
66 # define CONFIG_XILINX_EMACLITE 1
67 # define CONFIG_SYS_ENET
69 #if defined(XILINX_AXIEMAC_BASEADDR)
70 # define CONFIG_XILINX_AXIEMAC 1
71 # define CONFIG_SYS_ENET
77 #ifdef XILINX_GPIO_BASEADDR
78 # define CONFIG_XILINX_GPIO
79 # define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
82 /* interrupt controller */
83 #ifdef XILINX_INTC_BASEADDR
84 # define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
85 # define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
89 #if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
90 # define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
91 # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
95 #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
96 # define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
97 # define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
98 # ifndef CONFIG_SPL_BUILD
99 # define CONFIG_HW_WATCHDOG
100 # define CONFIG_XILINX_TB_WATCHDOG
104 #if !defined(CONFIG_OF_CONTROL) || \
105 (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL))
106 /* ddr sdram - main memory */
107 # define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
108 # define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
111 #define CONFIG_SYS_MALLOC_LEN 0xC0000
113 /* Stack location before relocation */
114 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
115 CONFIG_SYS_MALLOC_F_LEN)
118 * CFI flash memory layout - Example
119 * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
120 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
122 * SECT_SIZE = 0x20000; 128kB is one sector
123 * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
125 * 0x2200_0000 CONFIG_SYS_FLASH_BASE
127 * 0x2204_0000 CONFIG_ENV_ADDR
131 * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
136 # define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
137 # define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
138 # define CONFIG_SYS_FLASH_CFI 1
139 # define CONFIG_FLASH_CFI_DRIVER 1
141 # define CONFIG_SYS_FLASH_EMPTY_INFO 1
142 /* max number of memory banks */
143 # define CONFIG_SYS_MAX_FLASH_BANKS 1
144 /* max number of sectors on one chip */
145 # define CONFIG_SYS_MAX_FLASH_SECT 512
146 /* hardware flash protection */
147 # define CONFIG_SYS_FLASH_PROTECTION
148 /* use buffered writes (20x faster) */
149 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
151 # define CONFIG_ENV_IS_NOWHERE 1
152 # define CONFIG_ENV_SIZE 0x1000
153 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
155 # else /* FLASH && !RAMENV */
156 # define CONFIG_ENV_IS_IN_FLASH 1
157 /* 128K(one sector) for env */
158 # define CONFIG_ENV_SECT_SIZE 0x20000
159 # define CONFIG_ENV_ADDR \
160 (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
161 # define CONFIG_ENV_SIZE 0x20000
162 # endif /* FLASH && !RAMBOOT */
166 # define CONFIG_SYS_NO_FLASH 1
167 # define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
168 # define CONFIG_SPI 1
169 # define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
170 # define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
171 # define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
174 # define CONFIG_ENV_IS_NOWHERE 1
175 # define CONFIG_ENV_SIZE 0x1000
176 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
178 # else /* SPIFLASH && !RAMENV */
179 # define CONFIG_ENV_IS_IN_SPI_FLASH 1
180 # define CONFIG_ENV_SPI_MODE SPI_MODE_3
181 # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
182 # define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
183 /* 128K(two sectors) for env */
184 # define CONFIG_ENV_SECT_SIZE 0x10000
185 # define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
186 /* Warning: adjust the offset in respect of other flash content and size */
187 # define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
188 # endif /* SPIFLASH && !RAMBOOT */
189 #else /* !SPIFLASH */
192 # define CONFIG_SYS_NO_FLASH 1
193 # define CONFIG_ENV_IS_NOWHERE 1
194 # define CONFIG_ENV_SIZE 0x1000
195 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
196 #endif /* !SPIFLASH */
200 #ifdef XILINX_SYSACE_BASEADDR
201 # define CONFIG_SYSTEMACE
202 /* #define DEBUG_SYSTEMACE */
203 # define SYSTEMACE_CONFIG_FPGA
204 # define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
205 # define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
206 # define CONFIG_DOS_PARTITION
209 #if defined(XILINX_USE_ICACHE)
210 # define CONFIG_ICACHE
212 # undef CONFIG_ICACHE
215 #if defined(XILINX_USE_DCACHE)
216 # define CONFIG_DCACHE
218 # undef CONFIG_DCACHE
221 #ifndef XILINX_DCACHE_BYTE_SIZE
222 #define XILINX_DCACHE_BYTE_SIZE 32768
228 #define CONFIG_BOOTP_BOOTFILESIZE
229 #define CONFIG_BOOTP_BOOTPATH
230 #define CONFIG_BOOTP_GATEWAY
231 #define CONFIG_BOOTP_HOSTNAME
234 * Command line configuration.
236 #define CONFIG_CMD_ASKENV
237 #define CONFIG_CMD_IRQ
238 #define CONFIG_CMD_MFSL
240 #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
241 # define CONFIG_CMD_CACHE
243 # undef CONFIG_CMD_CACHE
246 #ifdef CONFIG_SYS_ENET
247 # define CONFIG_CMD_PING
248 # define CONFIG_CMD_DHCP
249 # define CONFIG_CMD_TFTPPUT
252 #if defined(CONFIG_SYSTEMACE)
253 # define CONFIG_CMD_EXT2
254 # define CONFIG_CMD_FAT
258 # define CONFIG_CMD_JFFS2
259 # define CONFIG_CMD_UBI
260 # undef CONFIG_CMD_UBIFS
262 # if !defined(RAMENV)
263 # define CONFIG_CMD_SAVES
267 #if defined(SPIFLASH)
268 # define CONFIG_CMD_SF
270 # if !defined(RAMENV)
271 # define CONFIG_CMD_SAVES
274 # undef CONFIG_CMD_JFFS2
275 # undef CONFIG_CMD_UBI
276 # undef CONFIG_CMD_UBIFS
280 #if defined(CONFIG_CMD_JFFS2)
281 # define CONFIG_MTD_PARTITIONS
284 #if defined(CONFIG_CMD_UBIFS)
285 # define CONFIG_CMD_UBI
289 #if defined(CONFIG_CMD_UBI)
290 # define CONFIG_MTD_PARTITIONS
291 # define CONFIG_RBTREE
294 #if defined(CONFIG_MTD_PARTITIONS)
296 #define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
297 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
298 #define CONFIG_FLASH_CFI_MTD
299 #define MTDIDS_DEFAULT "nor0=flash-0"
301 /* default mtd partition table */
302 #define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
303 "256k(env),3m(kernel),1m(romfs),"\
304 "1m(cramfs),-(jffs2)"
307 /* size of console buffer */
308 #define CONFIG_SYS_CBSIZE 512
309 /* print buffer size */
310 #define CONFIG_SYS_PBSIZE \
311 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
312 /* max number of command args */
313 #define CONFIG_SYS_MAXARGS 15
314 #define CONFIG_SYS_LONGHELP
315 /* default load address */
316 #define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
318 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
319 #define CONFIG_BOOTARGS "root=romfs"
320 #define CONFIG_HOSTNAME XILINX_BOARD_NAME
321 #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
322 #define CONFIG_IPADDR 192.168.0.3
323 #define CONFIG_SERVERIP 192.168.0.5
324 #define CONFIG_GATEWAYIP 192.168.0.1
326 /* architecture dependent code */
327 #define CONFIG_SYS_USR_EXCEP /* user exception */
329 #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
331 #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
333 "mtdparts=mtdparts=flash-0:"\
334 "256k(u-boot),256k(env),3m(kernel),"\
335 "1m(romfs),1m(cramfs),-(jffs2)\0"\
336 "nc=setenv stdout nc;"\
337 "setenv stdin nc\0" \
338 "serial=setenv stdout serial;"\
339 "setenv stdin serial\0"
341 #define CONFIG_CMDLINE_EDITING
343 #define CONFIG_NETCONSOLE
344 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
346 /* Use the HUSH parser */
347 #define CONFIG_SYS_HUSH_PARSER
349 /* Enable flat device tree support */
352 #define CONFIG_OF_LIBFDT 1
354 #if defined(CONFIG_XILINX_AXIEMAC)
355 # define CONFIG_MII 1
356 # define CONFIG_CMD_MII 1
357 # define CONFIG_PHY_GIGE 1
358 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
359 # define CONFIG_PHYLIB 1
360 # define CONFIG_PHY_ATHEROS 1
361 # define CONFIG_PHY_BROADCOM 1
362 # define CONFIG_PHY_DAVICOM 1
363 # define CONFIG_PHY_LXT 1
364 # define CONFIG_PHY_MARVELL 1
365 # define CONFIG_PHY_MICREL 1
366 # define CONFIG_PHY_NATSEMI 1
367 # define CONFIG_PHY_REALTEK 1
368 # define CONFIG_PHY_VITESSE 1
371 # undef CONFIG_CMD_MII
372 # undef CONFIG_PHYLIB
376 #define CONFIG_CMD_SPL
377 #define CONFIG_SPL_FRAMEWORK
378 #define CONFIG_SPL_LIBCOMMON_SUPPORT
379 #define CONFIG_SPL_LIBGENERIC_SUPPORT
380 #define CONFIG_SPL_SERIAL_SUPPORT
381 #define CONFIG_SPL_BOARD_INIT
383 #define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
385 #define CONFIG_SPL_RAM_DEVICE
386 #ifdef CONFIG_SYS_FLASH_BASE
387 # define CONFIG_SPL_NOR_SUPPORT
388 # define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
391 /* for booting directly linux */
392 #define CONFIG_SPL_OS_BOOT
394 #define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
396 #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
398 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
401 /* SP location before relocation, must use scratch RAM */
403 #define CONFIG_SYS_INIT_RAM_ADDR 0x0
404 /* BRAM size - will be generated */
405 #define CONFIG_SYS_INIT_RAM_SIZE 0x100000
407 # define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
408 CONFIG_SYS_INIT_RAM_SIZE - \
409 CONFIG_SYS_MALLOC_F_LEN)
411 /* Just for sure that there is a space for stack */
412 #define CONFIG_SPL_STACK_SIZE 0x100
414 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
416 #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
417 CONFIG_SYS_INIT_RAM_ADDR - \
418 CONFIG_SYS_MALLOC_F_LEN - \
419 CONFIG_SPL_STACK_SIZE)
421 #endif /* __CONFIG_H */