3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37 #define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
39 /* Do boardspecific init */
40 #define CONFIG_BOARD_EARLY_INIT_R 1
42 #define CONFIG_8xx_GCLK_FREQ 66000000
44 #define CFG_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
45 #define CFG_SMC_DPMEM_OFFSET 0x1fc0
46 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
48 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
50 #define CONFIG_BOOTCOUNT_LIMIT
52 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
54 #define CONFIG_BOARD_TYPES 1 /* support board types */
56 #define CONFIG_PREBOOT "echo;" \
57 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
60 #undef CONFIG_BOOTARGS
62 #define CONFIG_EXTRA_ENV_SETTINGS \
64 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
65 "nfsargs=setenv bootargs root=/dev/nfs rw " \
66 "nfsroot=${serverip}:${rootpath}\0" \
67 "ramargs=setenv bootargs root=/dev/ram rw\0" \
68 "addip=setenv bootargs ${bootargs} " \
69 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
70 ":${hostname}:${netdev}:off panic=1\0" \
71 "flash_nfs=run nfsargs addip;" \
72 "bootm ${kernel_addr}\0" \
73 "flash_self=run ramargs addip;" \
74 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
75 "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
76 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \
77 "bootm ${kernel_addr} - ${fdt_addr}\0" \
78 "rootpath=/opt/eldk/ppc_8xx\0" \
79 "bootfile=/tftpboot/mgsuvd/uImage\0" \
81 "kernel_addr=200000\0" \
82 "fdt_file=/tftpboot/mgsuvd/mgsuvd.dtb\0" \
83 "load=tftp 200000 ${u-boot}\0" \
84 "update=protect off f0000000 +${filesize};" \
85 "erase f0000000 +${filesize};" \
86 "cp.b 200000 f0000000 ${filesize};" \
87 "protect on f0000000 +${filesize}\0" \
89 #define CONFIG_BOOTCOMMAND "run flash_self"
91 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
92 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
94 #undef CONFIG_WATCHDOG /* watchdog disabled */
99 #define CONFIG_BOOTP_SUBNETMASK
100 #define CONFIG_BOOTP_GATEWAY
101 #define CONFIG_BOOTP_HOSTNAME
102 #define CONFIG_BOOTP_BOOTPATH
103 #define CONFIG_BOOTP_BOOTFILESIZE
105 #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
107 #define CONFIG_TIMESTAMP /* but print image timestmps */
110 * Command line configuration.
112 #include <config_cmd_default.h>
114 #define CONFIG_CMD_ASKENV
115 #define CONFIG_CMD_DHCP
116 #define CONFIG_CMD_DTT
117 #define CONFIG_CMD_EEPROM
118 #define CONFIG_CMD_I2C
119 #define CONFIG_CMD_NFS
120 #define CONFIG_CMD_PING
123 * Miscellaneous configurable options
125 #define CFG_LONGHELP /* undef to save memory */
126 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
128 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
129 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
130 #ifdef CFG_HUSH_PARSER
131 #define CFG_PROMPT_HUSH_PS2 "> "
134 #if defined(CONFIG_CMD_KGDB)
135 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
137 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
139 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
140 #define CFG_MAXARGS 16 /* max number of command args */
141 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
143 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
144 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
146 #define CFG_LOAD_ADDR 0x100000 /* default load address */
148 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
150 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
153 * Low Level Configuration Settings
154 * (address mappings, register initial values, etc.)
155 * You should know what you are doing if you make changes here.
157 /*-----------------------------------------------------------------------
158 * Internal Memory Mapped Register
160 #define CFG_IMMR 0xFFF00000
162 /*-----------------------------------------------------------------------
163 * Definitions for initial stack pointer and data area (in DPRAM)
165 #define CFG_INIT_RAM_ADDR CFG_IMMR
166 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
167 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
168 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
169 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
171 /*-----------------------------------------------------------------------
172 * Start addresses for the final memory configuration
173 * (Set up by the startup code)
174 * Please note that CFG_SDRAM_BASE _must_ start at 0
176 #define CFG_SDRAM_BASE 0x00000000
177 #define CFG_FLASH_BASE 0xf0000000
178 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
179 #define CFG_MONITOR_BASE CFG_FLASH_BASE
180 #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
183 * For booting Linux, the board info and command line data
184 * have to be in the first 8 MB of memory, since this is
185 * the maximum mapped by the Linux kernel during initialization.
187 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
189 /*-----------------------------------------------------------------------
192 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
193 #define CFG_FLASH_SIZE 32
194 #define CFG_FLASH_CFI
195 #define CONFIG_FLASH_CFI_DRIVER
196 #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
199 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
200 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
202 #define CONFIG_ENV_IS_IN_FLASH 1
203 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
204 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
205 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
207 /* Address and size of Redundant Environment Sector */
208 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
209 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
211 #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
213 /*-----------------------------------------------------------------------
214 * Cache Configuration
216 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
217 #if defined(CONFIG_CMD_KGDB)
218 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
221 /*-----------------------------------------------------------------------
222 * SYPCR - System Protection Control 11-9
223 * SYPCR can only be written once after reset!
224 *-----------------------------------------------------------------------
225 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
227 #define CFG_SYPCR 0xffffff89
229 /*-----------------------------------------------------------------------
230 * SIUMCR - SIU Module Configuration 11-6
231 *-----------------------------------------------------------------------
233 #define CFG_SIUMCR 0x00610480
235 /*-----------------------------------------------------------------------
236 * TBSCR - Time Base Status and Control 11-26
237 *-----------------------------------------------------------------------
238 * Clear Reference Interrupt Status, Timebase freezing enabled
240 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
242 /*-----------------------------------------------------------------------
243 * PISCR - Periodic Interrupt Status and Control 11-31
244 *-----------------------------------------------------------------------
245 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
247 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
249 /*-----------------------------------------------------------------------
250 * SCCR - System Clock and reset Control Register 15-27
251 *-----------------------------------------------------------------------
252 * Set clock output, timebase and RTC source and divider,
253 * power management and some other internal clocks
255 #define SCCR_MASK 0x01800000
256 #define CFG_SCCR 0x01800000
261 * Init Memory Controller:
263 * BR0/1 and OR0/1 (FLASH)
266 #define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
268 /* used to re-map FLASH both when starting from SRAM or FLASH:
269 * restrict access enough to keep SRAM working (if any)
270 * but not too much to meddle with FLASH accesses
272 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
273 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
276 * FLASH timing: Default value of OR0 after reset
278 #define CFG_OR0_PRELIM 0xfe000954
279 #define CFG_BR0_PRELIM 0xf0000401
282 * BR1 and OR1 (SDRAM)
285 #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
286 #define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
288 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
289 #define CFG_OR_TIMING_SDRAM 0x00000A00
291 #define CFG_OR1_PRELIM 0xfc000800
292 #define CFG_BR1_PRELIM (0x000000C0 | 0x01)
294 #define CFG_MPTPR 0x0200
295 /* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
296 1 Write loop Cycle (not used), 1 Timer Loop Cycle */
297 #define CFG_MBMR 0x10964111
298 #define CFG_MAR 0x00000088
301 * 4096 Rows from SDRAM example configuration
302 * 1000 factor s -> ms
303 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
304 * 4 Number of refresh cycles per period
305 * 64 Refresh cycle in ms per number of rows
307 #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
309 /* GPIO/PIGGY on CS3 initialization values
311 #define CFG_PIGGY_BASE (0x30000000)
312 #define CFG_OR3_PRELIM (0xfe000d24)
313 #define CFG_BR3_PRELIM (0x30000401)
316 * Internal Definitions
320 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
321 #define BOOTFLAG_WARM 0x02 /* Software reboot */
323 #define CONFIG_SCC3_ENET
324 #define CONFIG_ETHPRIME "SCC ETHERNET"
325 #define CONFIG_HAS_ETH0
327 /* pass open firmware flat tree */
328 #define CONFIG_OF_LIBFDT 1
329 #define CONFIG_OF_BOARD_SETUP 1
331 #define OF_CPU "PowerPC,866@0"
332 #define OF_SOC "soc@fff00000"
333 #define OF_TBCLK (bd->bi_busfreq / 4)
334 #define OF_STDOUT_PATH "/soc/cpm/serial@a80"
336 /* enable I2C and select the hardware/software driver */
337 #undef CONFIG_HARD_I2C /* I2C with hardware support */
338 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
339 #define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
340 #define CFG_I2C_SLAVE 0x7F
341 #define I2C_SOFT_DECLARATIONS
344 * Software (bit-bang) I2C driver configuration
346 #define I2C_BASE_DIR (CFG_PIGGY_BASE + 0x04)
347 #define I2C_BASE_PORT (CFG_PIGGY_BASE + 0x09)
351 #define SDA_CONF 0x1000
352 #define SCL_CONF 0x2000
354 #define I2C_ACTIVE do {} while (0)
355 #define I2C_TRISTATE do {} while (0)
356 #define I2C_READ i2c_soft_read_pin ()
357 #define I2C_SDA(bit) if(bit) { \
358 *(unsigned short *)(I2C_BASE_DIR) &= ~SDA_CONF; \
361 *(unsigned char *)(I2C_BASE_PORT) &= ~SDA_BIT; \
362 *(unsigned short *)(I2C_BASE_DIR) |= SDA_CONF; \
364 #define I2C_SCL(bit) if(bit) { \
365 *(unsigned short *)(I2C_BASE_DIR) &= ~SCL_CONF; \
368 *(unsigned char *)(I2C_BASE_PORT) &= ~SCL_BIT; \
369 *(unsigned short *)(I2C_BASE_DIR) |= SCL_CONF; \
371 #define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
373 #define CONFIG_I2C_MULTI_BUS 1
374 #define CONFIG_I2C_CMD_TREE 1
375 #define CFG_MAX_I2C_BUS 2
378 #define CFG_I2C_EEPROM_ADDR_LEN 1
379 #define CFG_I2C_MULTI_EEPROMS 1
380 #define CFG_EEPROM_PAGE_WRITE_ENABLE
381 #define CFG_EEPROM_PAGE_WRITE_BITS 3
382 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
384 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
385 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
386 #define CONFIG_DTT_SENSORS {0, 2, 4, 6} /* Sensor addresses */
387 #define CFG_DTT_MAX_TEMP 70
388 #define CFG_DTT_LOW_TEMP -30
389 #define CFG_DTT_HYSTERESIS 3
390 #define CFG_DTT_BUS_NUM (CFG_MAX_I2C_BUS)
392 #endif /* __CONFIG_H */