3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37 #define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
39 /* Do boardspecific init */
40 #define CONFIG_BOARD_EARLY_INIT_R 1
42 #define CONFIG_8xx_GCLK_FREQ 66000000
44 #define CFG_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
45 #define CFG_SMC_DPMEM_OFFSET 0x1fc0
46 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
48 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
50 #define CONFIG_BOOTCOUNT_LIMIT
52 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
54 #define CONFIG_BOARD_TYPES 1 /* support board types */
56 #define CONFIG_PREBOOT "echo;" \
57 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
60 #undef CONFIG_BOOTARGS
62 #define CONFIG_EXTRA_ENV_SETTINGS \
64 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
65 "nfsargs=setenv bootargs root=/dev/nfs rw " \
66 "nfsroot=${serverip}:${rootpath}\0" \
67 "ramargs=setenv bootargs root=/dev/ram rw\0" \
68 "addip=setenv bootargs ${bootargs} " \
69 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
70 ":${hostname}:${netdev}:off panic=1\0" \
71 "flash_nfs=run nfsargs addip;" \
72 "bootm ${kernel_addr}\0" \
73 "flash_self=run ramargs addip;" \
74 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
75 "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
76 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \
77 "bootm ${kernel_addr} - ${fdt_addr}\0" \
78 "rootpath=/opt/eldk/ppc_8xx\0" \
79 "bootfile=/tftpboot/mgsuvd/uImage\0" \
81 "kernel_addr=200000\0" \
82 "fdt_file=/tftpboot/mgsuvd/mgsuvd.dtb\0" \
83 "load=tftp 200000 ${u-boot}\0" \
84 "update=protect off f0000000 +${filesize};" \
85 "erase f0000000 +${filesize};" \
86 "cp.b 200000 f0000000 ${filesize};" \
87 "protect on f0000000 +${filesize}\0" \
89 #define CONFIG_BOOTCOMMAND "run flash_self"
91 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
92 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
94 #undef CONFIG_WATCHDOG /* watchdog disabled */
99 #define CONFIG_BOOTP_SUBNETMASK
100 #define CONFIG_BOOTP_GATEWAY
101 #define CONFIG_BOOTP_HOSTNAME
102 #define CONFIG_BOOTP_BOOTPATH
103 #define CONFIG_BOOTP_BOOTFILESIZE
105 #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
107 #define CONFIG_TIMESTAMP /* but print image timestmps */
110 * Command line configuration.
112 #include <config_cmd_default.h>
114 #define CONFIG_CMD_ASKENV
115 #define CONFIG_CMD_DHCP
116 #define CONFIG_CMD_I2C
117 #define CONFIG_CMD_NFS
118 #define CONFIG_CMD_PING
121 * Miscellaneous configurable options
123 #define CFG_LONGHELP /* undef to save memory */
124 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
126 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
127 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
128 #ifdef CFG_HUSH_PARSER
129 #define CFG_PROMPT_HUSH_PS2 "> "
132 #if defined(CONFIG_CMD_KGDB)
133 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
135 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
137 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
138 #define CFG_MAXARGS 16 /* max number of command args */
139 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
141 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
142 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
144 #define CFG_LOAD_ADDR 0x100000 /* default load address */
146 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
148 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
151 * Low Level Configuration Settings
152 * (address mappings, register initial values, etc.)
153 * You should know what you are doing if you make changes here.
155 /*-----------------------------------------------------------------------
156 * Internal Memory Mapped Register
158 #define CFG_IMMR 0xFFF00000
160 /*-----------------------------------------------------------------------
161 * Definitions for initial stack pointer and data area (in DPRAM)
163 #define CFG_INIT_RAM_ADDR CFG_IMMR
164 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
165 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
166 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
167 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
169 /*-----------------------------------------------------------------------
170 * Start addresses for the final memory configuration
171 * (Set up by the startup code)
172 * Please note that CFG_SDRAM_BASE _must_ start at 0
174 #define CFG_SDRAM_BASE 0x00000000
175 #define CFG_FLASH_BASE 0xf0000000
176 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
177 #define CFG_MONITOR_BASE CFG_FLASH_BASE
178 #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
181 * For booting Linux, the board info and command line data
182 * have to be in the first 8 MB of memory, since this is
183 * the maximum mapped by the Linux kernel during initialization.
185 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
187 /*-----------------------------------------------------------------------
190 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
191 #define CFG_FLASH_SIZE 32
192 #define CFG_FLASH_CFI
193 #define CONFIG_FLASH_CFI_DRIVER
194 #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
197 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
198 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
200 #define CONFIG_ENV_IS_IN_FLASH 1
201 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
202 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
203 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
205 /* Address and size of Redundant Environment Sector */
206 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
207 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
209 #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
211 /*-----------------------------------------------------------------------
212 * Cache Configuration
214 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
215 #if defined(CONFIG_CMD_KGDB)
216 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
219 /*-----------------------------------------------------------------------
220 * SYPCR - System Protection Control 11-9
221 * SYPCR can only be written once after reset!
222 *-----------------------------------------------------------------------
223 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
225 #define CFG_SYPCR 0xffffff89
227 /*-----------------------------------------------------------------------
228 * SIUMCR - SIU Module Configuration 11-6
229 *-----------------------------------------------------------------------
231 #define CFG_SIUMCR 0x00610480
233 /*-----------------------------------------------------------------------
234 * TBSCR - Time Base Status and Control 11-26
235 *-----------------------------------------------------------------------
236 * Clear Reference Interrupt Status, Timebase freezing enabled
238 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
240 /*-----------------------------------------------------------------------
241 * PISCR - Periodic Interrupt Status and Control 11-31
242 *-----------------------------------------------------------------------
243 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
245 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
247 /*-----------------------------------------------------------------------
248 * SCCR - System Clock and reset Control Register 15-27
249 *-----------------------------------------------------------------------
250 * Set clock output, timebase and RTC source and divider,
251 * power management and some other internal clocks
253 #define SCCR_MASK 0x01800000
254 #define CFG_SCCR 0x01800000
259 * Init Memory Controller:
261 * BR0/1 and OR0/1 (FLASH)
264 #define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
266 /* used to re-map FLASH both when starting from SRAM or FLASH:
267 * restrict access enough to keep SRAM working (if any)
268 * but not too much to meddle with FLASH accesses
270 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
271 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
274 * FLASH timing: Default value of OR0 after reset
276 #define CFG_OR0_PRELIM 0xfe000954
277 #define CFG_BR0_PRELIM 0xf0000401
280 * BR1 and OR1 (SDRAM)
283 #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
284 #define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
286 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
287 #define CFG_OR_TIMING_SDRAM 0x00000A00
289 #define CFG_OR1_PRELIM 0xfc000800
290 #define CFG_BR1_PRELIM (0x000000C0 | 0x01)
292 #define CFG_MPTPR 0x0200
293 /* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
294 1 Write loop Cycle (not used), 1 Timer Loop Cycle */
295 #define CFG_MBMR 0x10964111
296 #define CFG_MAR 0x00000088
299 * 4096 Rows from SDRAM example configuration
300 * 1000 factor s -> ms
301 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
302 * 4 Number of refresh cycles per period
303 * 64 Refresh cycle in ms per number of rows
305 #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
307 /* GPIO/PIGGY on CS3 initialization values
309 #define CFG_PIGGY_BASE (0x30000000)
310 #define CFG_OR3_PRELIM (0xfe000d24)
311 #define CFG_BR3_PRELIM (0x30000401)
314 * Internal Definitions
318 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
319 #define BOOTFLAG_WARM 0x02 /* Software reboot */
321 #define CONFIG_SCC3_ENET
322 #define CONFIG_ETHPRIME "SCC ETHERNET"
323 #define CONFIG_HAS_ETH0
325 /* pass open firmware flat tree */
326 #define CONFIG_OF_LIBFDT 1
327 #define CONFIG_OF_BOARD_SETUP 1
329 #define OF_CPU "PowerPC,866@0"
330 #define OF_SOC "soc@fff00000"
331 #define OF_TBCLK (bd->bi_busfreq / 4)
332 #define OF_STDOUT_PATH "/soc/cpm/serial@a80"
334 /* enable I2C and select the hardware/software driver */
335 #undef CONFIG_HARD_I2C /* I2C with hardware support */
336 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
337 #define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
338 #define CFG_I2C_SLAVE 0x7F
339 #define I2C_SOFT_DECLARATIONS
342 * Software (bit-bang) I2C driver configuration
344 #define I2C_BASE_DIR (CFG_PIGGY_BASE + 0x04)
345 #define I2C_BASE_PORT (CFG_PIGGY_BASE + 0x09)
349 #define SDA_CONF 0x1000
350 #define SCL_CONF 0x2000
352 #define I2C_ACTIVE do {} while (0)
353 #define I2C_TRISTATE do {} while (0)
354 #define I2C_READ i2c_soft_read_pin ()
355 #define I2C_SDA(bit) if(bit) { \
356 *(unsigned short *)(I2C_BASE_DIR) &= ~SDA_CONF; \
359 *(unsigned char *)(I2C_BASE_PORT) &= ~SDA_BIT; \
360 *(unsigned short *)(I2C_BASE_DIR) |= SDA_CONF; \
362 #define I2C_SCL(bit) if(bit) { \
363 *(unsigned short *)(I2C_BASE_DIR) &= ~SCL_CONF; \
366 *(unsigned char *)(I2C_BASE_PORT) &= ~SCL_BIT; \
367 *(unsigned short *)(I2C_BASE_DIR) |= SCL_CONF; \
369 #define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
371 #define CONFIG_I2C_MULTI_BUS 1
372 #define CONFIG_I2C_CMD_TREE 1
373 #define CFG_MAX_I2C_BUS 2
376 #endif /* __CONFIG_H */