3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC8247 1
33 #define CONFIG_MPC8272_FAMILY 1
34 #define CONFIG_MGCOGE 1
36 #define CONFIG_CPM2 1 /* Has a CPM2 */
38 /* include common defines/options for all Keymile boards */
39 #include "keymile-common.h"
42 * Select serial console configuration
44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
48 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
49 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
50 #undef CONFIG_CONS_NONE /* It's not on external UART */
51 #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
54 * Select ethernet configuration
56 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
57 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
60 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
61 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
64 #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
65 #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
66 #undef CONFIG_ETHER_NONE /* No external Ethernet */
67 #define CONFIG_NET_MULTI 1
69 #define CONFIG_ETHER_INDEX 4
70 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000
72 # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
74 #ifndef CONFIG_8260_CLKIN
75 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
79 * Default environment settings
81 #define CONFIG_EXTRA_ENV_SETTINGS \
83 "u-boot_addr=100000\0" \
84 "kernel_addr=200000\0" \
86 "rootpath=/opt/eldk-4.2/ppc_82xx\0" \
87 "u-boot=/tftpboot/mgcoge/u-boot.bin\0" \
88 "bootfile=/tftpboot/mgcoge/uImage\0" \
89 "fdt_file=/tftpboot/mgcoge/mgcoge.dtb\0" \
90 "load=tftp ${u-boot_addr} ${u-boot}\0" \
91 "update=prot off fe000000 fe03ffff; era fe000000 fe03ffff; " \
92 "cp.b ${u-boot_addr} fe000000 ${filesize};" \
93 "prot on fe000000 fe03ffff\0" \
94 "ramargs=setenv bootargs root=/dev/ram rw\0" \
95 "nfsargs=setenv bootargs root=/dev/nfs rw " \
96 "nfsroot=${serverip}:${rootpath}\0" \
97 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
98 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
99 "addip=setenv bootargs ${bootargs} " \
100 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
101 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
102 "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
103 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \
104 "bootm ${kernel_addr} - ${fdt_addr}\0" \
105 "net_self=tftp ${kernel_addr} ${bootfile}; " \
106 "tftp ${fdt_addr} ${fdt_file}; " \
107 "tftp ${ramdisk_addr} ${ramdisk_file}; " \
108 "run ramargs addip; " \
109 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
112 #define CONFIG_SYS_SDRAM_BASE 0x00000000
113 #define CONFIG_SYS_FLASH_BASE 0xFE000000
114 #define CONFIG_SYS_FLASH_SIZE 32
115 #define CONFIG_SYS_FLASH_CFI
116 #define CONFIG_FLASH_CFI_DRIVER
117 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
118 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
120 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
121 #define CONFIG_SYS_FLASH_SIZE_1 64
123 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
125 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
126 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
127 #define CONFIG_SYS_RAMBOOT
130 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
132 #define CONFIG_ENV_IS_IN_FLASH
134 #ifdef CONFIG_ENV_IS_IN_FLASH
135 #define CONFIG_ENV_SECT_SIZE 0x20000
136 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
137 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
139 /* Address and size of Redundant Environment Sector */
140 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
141 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
142 #endif /* CONFIG_ENV_IS_IN_FLASH */
144 /* enable I2C and select the hardware/software driver */
145 #undef CONFIG_HARD_I2C /* I2C with hardware support */
146 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
147 #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
148 #define CONFIG_SYS_I2C_SLAVE 0x7F
151 * Software (bit-bang) I2C driver configuration
154 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
155 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
156 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
157 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
158 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
159 else iop->pdat &= ~0x00010000
160 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
161 else iop->pdat &= ~0x00020000
162 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
164 #define CONFIG_I2C_MULTI_BUS 1
165 #define CONFIG_I2C_CMD_TREE 1
166 #define CONFIG_SYS_MAX_I2C_BUS 2
167 #define CONFIG_SYS_I2C_INIT_BOARD 1
168 #define CONFIG_I2C_MUX 1
171 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
172 #define CONFIG_SYS_I2C_MULTI_EEPROMS 1
173 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
174 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
177 /* Support the IVM EEprom */
178 #define CONFIG_SYS_IVM_EEPROM_ADR 0x50
179 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
180 #define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100
182 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
183 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
184 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
185 #define CONFIG_SYS_DTT_MAX_TEMP 70
186 #define CONFIG_SYS_DTT_LOW_TEMP -30
187 #define CONFIG_SYS_DTT_HYSTERESIS 3
188 #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
190 #define CONFIG_SYS_IMMR 0xF0000000
192 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
193 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
194 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
195 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
196 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
198 /* Hard reset configuration word */
199 #define CONFIG_SYS_HRCW_MASTER 0x0604b211
202 #define CONFIG_SYS_HRCW_SLAVE1 0
203 #define CONFIG_SYS_HRCW_SLAVE2 0
204 #define CONFIG_SYS_HRCW_SLAVE3 0
205 #define CONFIG_SYS_HRCW_SLAVE4 0
206 #define CONFIG_SYS_HRCW_SLAVE5 0
207 #define CONFIG_SYS_HRCW_SLAVE6 0
208 #define CONFIG_SYS_HRCW_SLAVE7 0
210 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
211 #define BOOTFLAG_WARM 0x02 /* Software reboot */
213 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
214 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
216 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
217 #if defined(CONFIG_CMD_KGDB)
218 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
221 #define CONFIG_SYS_HID0_INIT 0
222 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
224 #define CONFIG_SYS_HID2 0
226 #define CONFIG_SYS_SIUMCR 0x4020c200
227 #define CONFIG_SYS_SYPCR 0xFFFFFFC3
228 #define CONFIG_SYS_BCR 0x10000000
229 #define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
231 /*-----------------------------------------------------------------------
232 * RMR - Reset Mode Register 5-5
233 *-----------------------------------------------------------------------
234 * turn on Checkstop Reset Enable
236 #define CONFIG_SYS_RMR 0
238 /*-----------------------------------------------------------------------
239 * TMCNTSC - Time Counter Status and Control 4-40
240 *-----------------------------------------------------------------------
241 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
242 * and enable Time Counter
244 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
246 /*-----------------------------------------------------------------------
247 * PISCR - Periodic Interrupt Status and Control 4-42
248 *-----------------------------------------------------------------------
249 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
252 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
254 /*-----------------------------------------------------------------------
255 * RCCR - RISC Controller Configuration 13-7
256 *-----------------------------------------------------------------------
258 #define CONFIG_SYS_RCCR 0
261 * Init Memory Controller:
263 * Bank Bus Machine PortSz Device
264 * ---- --- ------- ------ ------
265 * 0 60x GPCM 8 bit FLASH
266 * 1 60x SDRAM 32 bit SDRAM
267 * 3 60x GPCM 8 bit GPIO/PIGGY
268 * 5 60x GPCM 16 bit CFG-Flash
273 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
278 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
285 /* Bank 1 - 60x bus SDRAM
287 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
288 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
290 #define CONFIG_SYS_MPTPR 0x1800
292 /*-----------------------------------------------------------------------------
293 * Address for Mode Register Set (MRS) command
294 *-----------------------------------------------------------------------------
296 #define CONFIG_SYS_MRS_OFFS 0x00000110
297 #define CONFIG_SYS_PSRT 0x0e
299 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
304 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
306 /* SDRAM initialization values
309 #define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
311 ORxS_ROWST_PBI0_A7 |\
314 #define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
315 PSDMR_BSMA_A14_A16 |\
316 PSDMR_SDA10_PBI0_A9 |\
324 /* GPIO/PIGGY on CS3 initialization values
326 #define CONFIG_SYS_PIGGY_BASE 0x30000000
327 #define CONFIG_SYS_PIGGY_SIZE 128
329 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
330 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
332 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
333 ORxG_CSNT | ORxG_ACS_DIV2 |\
334 ORxG_SCY_3_CLK | ORxG_TRLX )
336 /* CFG-Flash on CS5 initialization values
338 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
339 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
341 #define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1) |\
342 ORxG_CSNT | ORxG_ACS_DIV2 |\
343 ORxG_SCY_5_CLK | ORxG_TRLX )
345 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
347 /* pass open firmware flat tree */
349 #define CONFIG_OF_LIBFDT 1
350 #define CONFIG_OF_BOARD_SETUP 1
352 #define OF_CPU "PowerPC,8247@0"
353 #define OF_SOC "soc@f0000000"
354 #define OF_TBCLK (bd->bi_busfreq / 4)
355 #define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
357 #endif /* __CONFIG_H */