3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC8247 1
33 #define CONFIG_MPC8272_FAMILY 1
34 #define CONFIG_MGCOGE 1
35 #define CONFIG_HOSTNAME mgcoge
37 #define CONFIG_CPM2 1 /* Has a CPM2 */
39 /* include common defines/options for all Keymile boards */
40 #include "keymile-common.h"
43 * Select serial console configuration
45 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
46 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
49 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
50 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
51 #undef CONFIG_CONS_NONE /* It's not on external UART */
52 #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
53 #define CONFIG_SYS_SMC_RXBUFLEN 128
54 #define CONFIG_SYS_MAXIDLE 10
57 * Select ethernet configuration
59 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
60 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
63 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
64 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
67 #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
68 #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
69 #undef CONFIG_ETHER_NONE /* No external Ethernet */
70 #define CONFIG_NET_MULTI 1
72 #define CONFIG_ETHER_INDEX 4
73 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000
75 # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
77 #ifndef CONFIG_8260_CLKIN
78 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
81 #define BOOTFLASH_START FE000000
82 #define CONFIG_PRAM 512 /* protected RAM [KBytes] */
84 #define MTDIDS_DEFAULT "nor0=boot,nor1=app"
85 #define MTDPARTS_DEFAULT \
86 "mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \
87 "app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)"
90 * Default environment settings
92 #define CONFIG_EXTRA_ENV_SETTINGS \
94 "u-boot_addr=100000\0" \
95 "kernel_addr=200000\0" \
97 "rootpath=/opt/eldk-4.2/ppc_82xx\0" \
98 "u-boot=/tftpboot/mgcoge/u-boot.bin\0" \
99 "bootfile=/tftpboot/mgcoge/uImage\0" \
100 "fdt_file=/tftpboot/mgcoge/mgcoge.dtb\0" \
101 "load=tftp ${u-boot_addr} ${u-boot}\0" \
102 "update=prot off fe000000 fe03ffff; era fe000000 fe03ffff; " \
103 "cp.b ${u-boot_addr} fe000000 ${filesize};" \
104 "prot on fe000000 fe03ffff\0" \
105 "ramargs=setenv bootargs root=/dev/ram rw\0" \
106 "nfsargs=setenv bootargs root=/dev/nfs rw " \
107 "nfsroot=${serverip}:${rootpath}\0" \
108 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
109 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
110 "addip=setenv bootargs ${bootargs} " \
111 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
112 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
113 "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
114 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \
115 "bootm ${kernel_addr} - ${fdt_addr}\0" \
116 "net_self=tftp ${kernel_addr} ${bootfile}; " \
117 "tftp ${fdt_addr} ${fdt_file}; " \
118 "tftp ${ramdisk_addr} ${ramdisk_file}; " \
119 "run ramargs addip; " \
120 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
121 "EEprom_ivm=pca9544a:70:4 \0" \
122 "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
125 #define CONFIG_SYS_SDRAM_BASE 0x00000000
126 #define CONFIG_SYS_FLASH_BASE 0xFE000000
127 #define CONFIG_SYS_FLASH_SIZE 32
128 #define CONFIG_SYS_FLASH_CFI
129 #define CONFIG_FLASH_CFI_DRIVER
130 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
131 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
133 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
134 #define CONFIG_SYS_FLASH_SIZE_1 64
136 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
138 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
139 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
140 #define CONFIG_SYS_RAMBOOT
143 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384KB for Monitor */
145 #define CONFIG_ENV_IS_IN_FLASH
147 #ifdef CONFIG_ENV_IS_IN_FLASH
148 #define CONFIG_ENV_SECT_SIZE 0x4000
149 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
150 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
152 /* Address and size of Redundant Environment Sector */
153 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
154 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
155 #endif /* CONFIG_ENV_IS_IN_FLASH */
156 #define CONFIG_ENV_BUFFER_PRINT 1
158 /* enable I2C and select the hardware/software driver */
159 #undef CONFIG_HARD_I2C /* I2C with hardware support */
160 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
161 #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
162 #define CONFIG_SYS_I2C_SLAVE 0x7F
165 * Software (bit-bang) I2C driver configuration
168 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
169 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
170 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
171 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
172 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
173 else iop->pdat &= ~0x00010000
174 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
175 else iop->pdat &= ~0x00020000
176 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
178 #define CONFIG_I2C_MULTI_BUS 1
179 #define CONFIG_I2C_CMD_TREE 1
180 #define CONFIG_SYS_MAX_I2C_BUS 2
181 #define CONFIG_SYS_I2C_INIT_BOARD 1
182 #define CONFIG_I2C_MUX 1
185 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
186 #define CONFIG_SYS_I2C_MULTI_EEPROMS 1
187 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
188 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
189 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
191 /* Support the IVM EEprom */
192 #define CONFIG_SYS_IVM_EEPROM_ADR 0x50
193 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
194 #define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100
196 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
197 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
198 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
199 #define CONFIG_SYS_DTT_MAX_TEMP 70
200 #define CONFIG_SYS_DTT_LOW_TEMP -30
201 #define CONFIG_SYS_DTT_HYSTERESIS 3
202 #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
204 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
206 #define CONFIG_SYS_IMMR 0xF0000000
208 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
209 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
210 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
211 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
212 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
214 /* Hard reset configuration word */
215 #define CONFIG_SYS_HRCW_MASTER 0x0604b211
218 #define CONFIG_SYS_HRCW_SLAVE1 0
219 #define CONFIG_SYS_HRCW_SLAVE2 0
220 #define CONFIG_SYS_HRCW_SLAVE3 0
221 #define CONFIG_SYS_HRCW_SLAVE4 0
222 #define CONFIG_SYS_HRCW_SLAVE5 0
223 #define CONFIG_SYS_HRCW_SLAVE6 0
224 #define CONFIG_SYS_HRCW_SLAVE7 0
226 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
227 #define BOOTFLAG_WARM 0x02 /* Software reboot */
229 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
230 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
232 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
233 #if defined(CONFIG_CMD_KGDB)
234 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
237 #define CONFIG_SYS_HID0_INIT 0
238 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
240 #define CONFIG_SYS_HID2 0
242 #define CONFIG_SYS_SIUMCR 0x4020c200
243 #define CONFIG_SYS_SYPCR 0xFFFFFFC3
244 #define CONFIG_SYS_BCR 0x10000000
245 #define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
247 /*-----------------------------------------------------------------------
248 * RMR - Reset Mode Register 5-5
249 *-----------------------------------------------------------------------
250 * turn on Checkstop Reset Enable
252 #define CONFIG_SYS_RMR 0
254 /*-----------------------------------------------------------------------
255 * TMCNTSC - Time Counter Status and Control 4-40
256 *-----------------------------------------------------------------------
257 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
258 * and enable Time Counter
260 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
262 /*-----------------------------------------------------------------------
263 * PISCR - Periodic Interrupt Status and Control 4-42
264 *-----------------------------------------------------------------------
265 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
268 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
270 /*-----------------------------------------------------------------------
271 * RCCR - RISC Controller Configuration 13-7
272 *-----------------------------------------------------------------------
274 #define CONFIG_SYS_RCCR 0
277 * Init Memory Controller:
279 * Bank Bus Machine PortSz Device
280 * ---- --- ------- ------ ------
281 * 0 60x GPCM 8 bit FLASH
282 * 1 60x SDRAM 32 bit SDRAM
283 * 3 60x GPCM 8 bit GPIO/PIGGY
284 * 5 60x GPCM 16 bit CFG-Flash
289 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
294 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
301 /* Bank 1 - 60x bus SDRAM
303 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
304 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
306 #define CONFIG_SYS_MPTPR 0x1800
308 /*-----------------------------------------------------------------------------
309 * Address for Mode Register Set (MRS) command
310 *-----------------------------------------------------------------------------
312 #define CONFIG_SYS_MRS_OFFS 0x00000110
313 #define CONFIG_SYS_PSRT 0x0e
315 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
320 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
322 /* SDRAM initialization values
325 #define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
327 ORxS_ROWST_PBI0_A7 |\
330 #define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
331 PSDMR_BSMA_A14_A16 |\
332 PSDMR_SDA10_PBI0_A9 |\
340 /* GPIO/PIGGY on CS3 initialization values
342 #define CONFIG_SYS_PIGGY_BASE 0x30000000
343 #define CONFIG_SYS_PIGGY_SIZE 128
345 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
346 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
348 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
349 ORxG_CSNT | ORxG_ACS_DIV2 |\
350 ORxG_SCY_3_CLK | ORxG_TRLX )
352 /* Board FPGA on CS4 initialization values
354 #define CONFIG_SYS_FPGA_BASE 0x40000000
355 #define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
357 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
358 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
360 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
361 ORxG_CSNT | ORxG_ACS_DIV2 |\
362 ORxG_SCY_3_CLK | ORxG_TRLX )
364 /* CFG-Flash on CS5 initialization values
366 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
367 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
369 #define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1) |\
370 ORxG_CSNT | ORxG_ACS_DIV2 |\
371 ORxG_SCY_5_CLK | ORxG_TRLX )
373 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
375 /* pass open firmware flat tree */
377 #define CONFIG_OF_LIBFDT 1
378 #define CONFIG_OF_BOARD_SETUP 1
380 #define OF_CPU "PowerPC,8247@0"
381 #define OF_SOC "soc@f0000000"
382 #define OF_TBCLK (bd->bi_busfreq / 4)
383 #define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
385 #endif /* __CONFIG_H */