2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /*************************************************************************
26 * (c) 2005 esd gmbh Hannover
30 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
32 *************************************************************************/
38 * High Level Configuration Options
42 #define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
43 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
44 #define CONFIG_ICECUBE 1 /* ... on IceCube board */
45 #define CONFIG_MECP5200 1 /* ... on MECP5200 board */
46 #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
48 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
50 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
51 #define BOOTFLAG_WARM 0x02 /* Software reboot */
54 * Serial console configuration
56 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
58 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
60 #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
62 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
65 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
68 #if 0 /* test-only !!! */
69 #define CONFIG_NET_MULTI 1
70 #define CONFIG_EEPRO100 1
71 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
72 #define CONFIG_NS8382X 1
80 #define CONFIG_MAC_PARTITION
81 #define CONFIG_DOS_PARTITION
85 #define CONFIG_USB_OHCI
86 #define CONFIG_USB_STORAGE
91 * Command line configuration.
93 #include <config_cmd_default.h>
95 #define CONFIG_CMD_EEPROM
96 #define CONFIG_CMD_FAT
97 #define CONFIG_CMD_EXT2
98 #define CONFIG_CMD_I2C
99 #define CONFIG_CMD_IDE
100 #define CONFIG_CMD_BSP
101 #define CONFIG_CMD_ELF
104 #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
105 # define CFG_LOWBOOT 1
106 # define CFG_LOWBOOT16 1
108 #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
109 # define CFG_LOWBOOT 1
110 # define CFG_LOWBOOT08 1
116 #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
118 #define CONFIG_PREBOOT "echo;" \
119 "echo Welcome to CBX-CPU5200 (mecp5200);" \
122 #undef CONFIG_BOOTARGS
124 #define CONFIG_EXTRA_ENV_SETTINGS \
126 "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
127 "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
128 "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
129 "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
130 "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
131 "loadaddr=01000000\0" \
132 "serverip=192.168.2.99\0" \
133 "gatewayip=10.0.0.79\0" \
135 "target=mecp5200.esd\0" \
136 "script=mecp5200.bat\0" \
137 "image=/tftpboot/vxWorks_mecp5200\0" \
138 "ipaddr=10.0.13.196\0" \
139 "netmask=255.255.0.0\0" \
142 #define CONFIG_BOOTCOMMAND "run flash_vxworks0"
144 #if defined(CONFIG_MPC5200)
146 * IPB Bus clocking configuration.
148 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
153 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
154 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
156 #define CFG_I2C_SPEED 86000 /* 100 kHz */
157 #define CFG_I2C_SLAVE 0x7F
160 * EEPROM configuration
162 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
163 #define CFG_I2C_EEPROM_ADDR_LEN 2
164 #define CFG_EEPROM_PAGE_WRITE_BITS 5
165 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
166 #define CFG_I2C_MULTI_EEPROMS 1
168 * Flash configuration
170 #define CFG_FLASH_BASE 0xFFC00000
171 #define CFG_FLASH_SIZE 0x00400000
172 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x003E0000)
173 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
174 #define CFG_MAX_FLASH_SECT 512
176 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
177 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
180 * Environment settings
182 #if 1 /* test-only */
183 #define CFG_ENV_IS_IN_FLASH 1
184 #define CFG_ENV_SIZE 0x10000
185 #define CFG_ENV_SECT_SIZE 0x10000
186 #define CONFIG_ENV_OVERWRITE 1
188 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
189 #define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
190 #define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/
191 /* total size of a CAT24WC32 is 8192 bytes */
192 #define CONFIG_ENV_OVERWRITE 1
195 #define CFG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
196 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
197 #define CFG_FLASH_PROTECTION 1 /* use hardware protection */
199 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
201 #define CFG_FLASH_INCREMENT 0x00400000 /* size of flash bank */
202 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
203 #define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */
209 #define CFG_MBAR 0xF0000000
210 #define CFG_SDRAM_BASE 0x00000000
211 #define CFG_DEFAULT_MBAR 0x80000000
213 /* Use SRAM until RAM will be available */
214 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
215 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
218 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
219 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
220 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
222 #define CFG_MONITOR_BASE TEXT_BASE
223 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
224 # define CFG_RAMBOOT 1
227 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
228 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
229 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
232 * Ethernet configuration
234 #define CONFIG_MPC5xxx_FEC 1
236 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
238 /* #define CONFIG_FEC_10MBIT 1 */
239 #define CONFIG_PHY_ADDR 0x00
240 #define CONFIG_UDP_CHECKSUM 1
246 #define CFG_GPS_PORT_CONFIG 0x01052444
249 * Miscellaneous configurable options
251 #define CFG_LONGHELP /* undef to save memory */
252 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
253 #if defined(CONFIG_CMD_KGDB)
254 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
256 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
258 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
259 #define CFG_MAXARGS 16 /* max number of command args */
260 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
262 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
263 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
265 #define CFG_LOAD_ADDR 0x100000 /* default load address */
267 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
269 #define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
271 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
272 #if defined(CONFIG_CMD_KGDB)
273 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
277 * Various low-level settings
279 #if defined(CONFIG_MPC5200)
280 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
281 #define CFG_HID0_FINAL HID0_ICE
283 #define CFG_HID0_INIT 0
284 #define CFG_HID0_FINAL 0
287 #define CFG_BOOTCS_START CFG_FLASH_BASE
288 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
289 #define CFG_BOOTCS_CFG 0x00085d00
291 #define CFG_CS0_START CFG_FLASH_BASE
292 #define CFG_CS0_SIZE CFG_FLASH_SIZE
294 #define CFG_CS1_START 0xfd000000
295 #define CFG_CS1_SIZE 0x00010000
296 #define CFG_CS1_CFG 0x10101410
298 #define CFG_CS_BURST 0x00000000
299 #define CFG_CS_DEADCYCLE 0x33333333
301 #define CFG_RESET_ADDRESS 0xff000000
303 /*-----------------------------------------------------------------------
305 *-----------------------------------------------------------------------
307 #define CONFIG_USB_CLOCK 0x0001BBBB
308 #define CONFIG_USB_CONFIG 0x00001000
310 /*-----------------------------------------------------------------------
311 * IDE/ATA stuff Supports IDE harddisk
312 *-----------------------------------------------------------------------
315 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
317 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
318 #undef CONFIG_IDE_LED /* LED for ide not supported */
320 #define CONFIG_IDE_RESET /* reset for ide supported */
321 #define CONFIG_IDE_PREINIT
323 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
324 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
326 #define CFG_ATA_IDE0_OFFSET 0x0000
328 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
330 /* Offset for data I/O */
331 #define CFG_ATA_DATA_OFFSET (0x0060)
333 /* Offset for normal register accesses */
334 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
336 /* Offset for alternate registers */
337 #define CFG_ATA_ALT_OFFSET (0x005C)
339 /* Interval between registers */
340 #define CFG_ATA_STRIDE 4
342 #endif /* __CONFIG_H */