Merge branch 'master' of http://git.denx.de/u-boot-sunxi
[oweals/u-boot.git] / include / configs / mecp5123.h
1 /*
2  * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3  * (C) Copyright 2009, DAVE Srl <www.dave.eu>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com
7  *
8  */
9
10 /*
11  * MECP5123 board configuration file
12  */
13
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16
17 #define CONFIG_MECP5123 1
18
19 /*
20  * Memory map for the MECP5123 board:
21  *
22  * 0x0000_0000 - 0x1FFF_FFFF    DDR RAM (512 MB)
23  * 0x3000_0000 - 0x3001_FFFF    SRAM (128 KB)
24  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
25  * 0x8200_0000 - 0x8200_FFFF    VPC-3 (64 KB)
26  * 0xFFC0_0000 - 0xFFFF_FFFF    NOR Boot FLASH (64 MB)
27  */
28
29 /*
30  * High Level Configuration Options
31  */
32 #define CONFIG_E300             1       /* E300 Family */
33
34 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
35
36 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
37
38 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f() */
39 #define CONFIG_MISC_INIT_R
40
41 #define CONFIG_SYS_IMMR                 0x80000000
42 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_IMMR+0x2100)
43
44 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
45 #define CONFIG_SYS_MEMTEST_END          0x00400000
46
47 /*
48  * DDR Setup - manually set all parameters as there's no SPD etc.
49  */
50 #define CONFIG_SYS_DDR_SIZE             512             /* MB */
51
52 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is sys memory*/
53 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
54 #define CONFIG_SYS_MAX_RAM_SIZE         0x20000000
55
56 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000036
57
58 /* DDR Controller Configuration
59  *
60  * SYS_CFG:
61  *      [31:31] MDDRC Soft Reset:       Diabled
62  *      [30:30] DRAM CKE pin:           Enabled
63  *      [29:29] DRAM CLK:               Enabled
64  *      [28:28] Command Mode:           Enabled (For initialization only)
65  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
66  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
67  *      [20:19] Read Test:              DON'T USE
68  *      [18:18] Self Refresh:           Enabled
69  *      [17:17] 16bit Mode:             Disabled
70  *      [16:13] Ready Delay:            2
71  *      [12:12] Half DQS Delay:         Disabled
72  *      [11:11] Quarter DQS Delay:      Disabled
73  *      [10:08] Write Delay:            2
74  *      [07:07] Early ODT:              Disabled
75  *      [06:06] On DIE Termination:     Disabled
76  *      [05:05] FIFO Overflow Clear:    DON'T USE here
77  *      [04:04] FIFO Underflow Clear:   DON'T USE here
78  *      [03:03] FIFO Overflow Pending:  DON'T USE here
79  *      [02:02] FIFO Underlfow Pending: DON'T USE here
80  *      [01:01] FIFO Overlfow Enabled:  Enabled
81  *      [00:00] FIFO Underflow Enabled: Enabled
82  * TIME_CFG0
83  *      [31:16] DRAM Refresh Time:      0 CSB clocks
84  *      [15:8]  DRAM Command Time:      0 CSB clocks
85  *      [07:00] DRAM Precharge Time:    0 CSB clocks
86  * TIME_CFG1
87  *      [31:26] DRAM tRFC:
88  *      [25:21] DRAM tWR1:
89  *      [20:17] DRAM tWRT1:
90  *      [16:11] DRAM tDRR:
91  *      [10:05] DRAM tRC:
92  *      [04:00] DRAM tRAS:
93  * TIME_CFG2
94  *      [31:28] DRAM tRCD:
95  *      [27:23] DRAM tFAW:
96  *      [22:19] DRAM tRTW1:
97  *      [18:15] DRAM tCCD:
98  *      [14:10] DRAM tRTP:
99  *      [09:05] DRAM tRP:
100  *      [04:00] DRAM tRPA
101  */
102 #define CONFIG_SYS_MDDRC_SYS_CFG         0xEA804A00
103 #define CONFIG_SYS_MDDRC_TIME_CFG0       0x06183D2E
104 #define CONFIG_SYS_MDDRC_TIME_CFG1       0x68EC1168
105 #define CONFIG_SYS_MDDRC_TIME_CFG2       0x34310864
106
107 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
108 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
109 #define CONFIG_SYS_DDRCMD_EM2           0x01020000
110 #define CONFIG_SYS_DDRCMD_EM3           0x01030000
111 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010000
112 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
113 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
114 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   0x01010780
115
116 /* DDR Priority Manager Configuration */
117 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
118 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
119 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
120 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
121 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
122 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
123 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
124 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
125 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
126 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
127 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
128 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
129 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
130 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
131 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
132 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
133 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
134 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
135 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
136 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
137 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
138 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
139 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
140
141 /*
142  * NOR FLASH on the Local Bus
143  */
144 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
145 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
146
147 #define CONFIG_SYS_FLASH_BASE           0xFFC00000      /* start of FLASH */
148 #define CONFIG_SYS_FLASH_SIZE           0x00400000      /* max flash size */
149
150 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
151 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
152 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
153 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
154
155 #undef CONFIG_SYS_FLASH_CHECKSUM
156
157 /*
158  * NAND FLASH
159  * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
160  */
161 #define CONFIG_CMD_NAND
162 #define CONFIG_NAND_MPC5121_NFC
163 #define CONFIG_SYS_NAND_BASE            0x40000000
164 #define CONFIG_SYS_MAX_NAND_DEVICE      1
165
166 /*
167  * Configuration parameters for MPC5121 NAND driver
168  */
169 #define CONFIG_FSL_NFC_WIDTH            1
170 #define CONFIG_FSL_NFC_WRITE_SIZE       2048
171 #define CONFIG_FSL_NFC_SPARE_SIZE       64
172 #define CONFIG_FSL_NFC_CHIPS            1
173
174 #define CONFIG_SYS_SRAM_BASE            0x30000000
175 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
176
177 /* Initialize Local Window for NOR FLASH access */
178 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
179 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
180
181 /* ALE active low, data size 4bytes */
182 #define CONFIG_SYS_CS0_CFG              0x05051150
183
184 /* Use not alternative CS timing */
185 #define CONFIG_SYS_CS_ALETIMING         0x00000000
186
187 /* ALE active low, data size 4bytes */
188 #define CONFIG_SYS_CS1_CFG              0x1f1f3090
189 #define CONFIG_SYS_VPC3_BASE            0x82000000      /* start of VPC3 space */
190 #define CONFIG_SYS_VPC3_SIZE            0x00010000      /* max VPC3 size */
191 /* Initialize Local Window for VPC3 access */
192 #define CONFIG_SYS_CS1_START            CONFIG_SYS_VPC3_BASE
193 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_VPC3_SIZE
194
195 /* Use SRAM for initial stack */
196 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE /* Init RAM addr */
197 #define CONFIG_SYS_INIT_RAM_SIZE                CONFIG_SYS_SRAM_SIZE
198
199 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
200 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
201
202 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* Start of monitor */
203 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Monitor length */
204 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024) /* Malloc size */
205
206 /*
207  * Serial Port
208  */
209 #define CONFIG_CONS_INDEX     1
210
211 /*
212  * Serial console configuration
213  */
214 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
215 #define CONFIG_SYS_PSC3
216 #if CONFIG_PSC_CONSOLE != 3
217 #error CONFIG_PSC_CONSOLE must be 3
218 #endif
219 #define CONFIG_BAUDRATE         9600    /* ... at 9600 bps */
220 #define CONFIG_SYS_BAUDRATE_TABLE  \
221         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
222
223 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC3_TX_SIZE
224 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC3_TX_ADDR
225 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC3_RX_SIZE
226 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC3_RX_ADDR
227
228 /*
229  * Clocks in use
230  */
231 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
232                          CLOCK_SCCR1_LPC_EN |                           \
233                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
234                          CLOCK_SCCR1_PSCFIFO_EN |                       \
235                          CLOCK_SCCR1_DDR_EN |                           \
236                          CLOCK_SCCR1_FEC_EN |                           \
237                          CLOCK_SCCR1_NFC_EN |                           \
238                          CLOCK_SCCR1_PCI_EN |                           \
239                          CLOCK_SCCR1_TPR_EN)
240
241 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN |   \
242                          CLOCK_SCCR2_I2C_EN)
243
244 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
245
246 /* I2C */
247 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
248 #define CONFIG_I2C_MULTI_BUS
249 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed */
250 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* slave address */
251
252 /*
253  * IIM - IC Identification Module
254  */
255 #undef CONFIG_FSL_IIM
256
257 /*
258  * EEPROM configuration
259  */
260 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* 16-bit EEPROM address */
261 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* Atmel: AT24C32A-10TQ-2.7 */
262 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10        /* 10ms of delay */
263 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5     /* 32-Byte Page Write Mode */
264 #define CONFIG_SYS_EEPROM_WREN                  /* Use EEPROM write protect */
265
266 /*
267  * Ethernet configuration
268  */
269 #define CONFIG_MPC512x_FEC      1
270 #define CONFIG_PHY_ADDR         0x1
271 #define CONFIG_MII              1       /* MII PHY management           */
272 #define CONFIG_FEC_AN_TIMEOUT   1
273 #define CONFIG_HAS_ETH0
274
275 /*
276  * Configure on-board RTC
277  */
278 #define CONFIG_SYS_RTC_BUS_NUM  0x01
279 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
280 #define CONFIG_RTC_RX8025
281
282 /*
283  * Environment
284  */
285 #define CONFIG_ENV_IS_IN_EEPROM         /* Store env in I2C EEPROM      */
286 #define CONFIG_ENV_SIZE         0x1000
287 #define CONFIG_ENV_OFFSET       0x0000  /* environment starts here      */
288
289 #define CONFIG_LOADS_ECHO               /* echo on for serial download  */
290 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change        */
291
292 #define CONFIG_CMD_REGINFO
293 #define CONFIG_CMD_EEPROM
294 #define CONFIG_CMD_DATE
295 #undef CONFIG_CMD_FUSE
296 #undef CONFIG_CMD_IDE
297 #define CONFIG_CMD_JFFS2
298 #define CONFIG_DOS_PARTITION
299
300 /*
301  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
302  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
303  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
304  * to chapter 36 of the MPC5121e Reference Manual.
305  */
306 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
307 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
308
309  /*
310  * Miscellaneous configurable options
311  */
312 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
313 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
314
315 #ifdef CONFIG_CMD_KGDB
316 # define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
317 #else
318 # define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
319 #endif
320
321 /* Print Buffer Size */
322 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
323                                  sizeof(CONFIG_SYS_PROMPT) + 16)
324 /* max number of command args */
325 #define CONFIG_SYS_MAXARGS      32
326 /* Boot Argument Buffer Size */
327 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
328
329 /*
330  * For booting Linux, the board info and command line data
331  * have to be in the first 256 MB of memory, since this is
332  * the maximum mapped by the Linux kernel during initialization.
333  */
334 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Linux initial memory map */
335
336 /* Cache Configuration */
337 #define CONFIG_SYS_DCACHE_SIZE          32768
338 #define CONFIG_SYS_CACHELINE_SIZE       32
339 #ifdef CONFIG_CMD_KGDB
340 #define CONFIG_SYS_CACHELINE_SHIFT      5
341 #endif
342
343 #define CONFIG_SYS_HID0_INIT    0x000000000
344 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_MACHINE_CHECK
345 #define CONFIG_SYS_HID2         HID2_HBE
346
347 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
348
349 #ifdef CONFIG_CMD_KGDB
350 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
351 #endif
352
353 /*
354  * Environment Configuration
355  */
356 #define CONFIG_TIMESTAMP
357
358 #define CONFIG_HOSTNAME         mecp512x
359 #define CONFIG_BOOTFILE         "/tftpboot/mecp512x/uImage"
360 #define CONFIG_ROOTPATH         "/tftpboot/mecp512x/target_root"
361
362 #define CONFIG_LOADADDR         400000  /* def. location for tftp and bootm */
363
364 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs*/
365
366 #define CONFIG_PREBOOT  "echo;" \
367         "echo Welcome to MECP5123" \
368         "echo"
369
370 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
371         "u-boot_addr_r=200000\0"                                        \
372         "kernel_addr_r=600000\0"                                        \
373         "fdt_addr_r=880000\0"                                           \
374         "ramdisk_addr_r=900000\0"                                       \
375         "u-boot_addr=FFF00000\0"                                        \
376         "kernel_addr=FFC40000\0"                                        \
377         "fdt_addr=FFEC0000\0"                                           \
378         "ramdisk_addr=FC040000\0"                                       \
379         "ramdiskfile=/tftpboot/mecp512x/uRamdisk\0"                     \
380         "u-boot=/tftpboot/mecp512x/u-boot.bin\0"                        \
381         "bootfile=/tftpboot/mecp512x/uImage\0"                          \
382         "fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0"                     \
383         "rootpath=/tftpboot/mecp512x/target_root\n"                     \
384         "netdev=eth0\0"                                                 \
385         "consdev=ttyPSC0\0"                                             \
386         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
387                 "nfsroot=${serverip}:${rootpath}\0"                     \
388         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
389         "addip=setenv bootargs ${bootargs} "                            \
390                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
391                 ":${hostname}:${netdev}:off panic=1\0"                  \
392         "addtty=setenv bootargs ${bootargs} "                           \
393                 "console=${consdev},${baudrate}\0"                      \
394         "flash_nfs=run nfsargs addip addtty;"                           \
395                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
396         "flash_self=run ramargs addip addtty;"                          \
397                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
398         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
399                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
400                 "run nfsargs addip addtty;"                             \
401                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
402         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
403                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
404                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
405                 "run ramargs addip addtty;"                             \
406                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
407         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
408         "update=protect off ${u-boot_addr} +${filesize};"               \
409                 "era ${u-boot_addr} +${filesize};"                      \
410                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
411         "upd=run load update\0"                                         \
412         ""
413
414 #define CONFIG_BOOTCOMMAND      "run flash_self"
415
416 #define OF_CPU                  "PowerPC,5121@0"
417 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
418 #define OF_TBCLK                (bd->bi_busfreq / 4)
419 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
420
421 #endif  /* __CONFIG_H */