include/configs/mecp5123.h

   1 /*
   2  * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
   3  * (C) Copyright 2009, DAVE Srl <www.dave.eu>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com
  24  *
  25  */
  26
  27 /*
  28  * MECP5123 board configuration file
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 #define CONFIG_MECP5123 1
  35 /*
  36  * Memory map for the MECP5123 board:
  37  *
  38  * 0x0000_0000 - 0x1FFF_FFFF    DDR RAM (512 MB)
  39  * 0x3000_0000 - 0x3001_FFFF    SRAM (128 KB)
  40  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  41  * 0x8200_0000 - 0x8200_FFFF    VPC-3 (64 KB)
  42  * 0xFFC0_0000 - 0xFFFF_FFFF    NOR Boot FLASH (64 MB)
  43  */
  44
  45 /*
  46  * High Level Configuration Options
  47  */
  48 #define CONFIG_E300             1       /* E300 Family */
  49 #define CONFIG_MPC512X          1       /* MPC512X family */
  50
  51 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  52
  53 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
  54
  55 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f() */
  56 #define CONFIG_MISC_INIT_R
  57
  58 #define CONFIG_SYS_IMMR                 0x80000000
  59 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_IMMR+0x2100)
  60
  61 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  62 #define CONFIG_SYS_MEMTEST_END          0x00400000
  63
  64 /*
  65  * DDR Setup - manually set all parameters as there's no SPD etc.
  66  */
  67 #define CONFIG_SYS_DDR_SIZE             512             /* MB */
  68
  69 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is sys memory*/
  70 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  71 #define CONFIG_SYS_MAX_RAM_SIZE         0x20000000
  72
  73 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000036
  74
  75 /* DDR Controller Configuration
  76  *
  77  * SYS_CFG:
  78  *      [31:31] MDDRC Soft Reset:       Diabled
  79  *      [30:30] DRAM CKE pin:           Enabled
  80  *      [29:29] DRAM CLK:               Enabled
  81  *      [28:28] Command Mode:           Enabled (For initialization only)
  82  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  83  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  84  *      [20:19] Read Test:              DON'T USE
  85  *      [18:18] Self Refresh:           Enabled
  86  *      [17:17] 16bit Mode:             Disabled
  87  *      [16:13] Ready Delay:            2
  88  *      [12:12] Half DQS Delay:         Disabled
  89  *      [11:11] Quarter DQS Delay:      Disabled
  90  *      [10:08] Write Delay:            2
  91  *      [07:07] Early ODT:              Disabled
  92  *      [06:06] On DIE Termination:     Disabled
  93  *      [05:05] FIFO Overflow Clear:    DON'T USE here
  94  *      [04:04] FIFO Underflow Clear:   DON'T USE here
  95  *      [03:03] FIFO Overflow Pending:  DON'T USE here
  96  *      [02:02] FIFO Underlfow Pending: DON'T USE here
  97  *      [01:01] FIFO Overlfow Enabled:  Enabled
  98  *      [00:00] FIFO Underflow Enabled: Enabled
  99  * TIME_CFG0
 100  *      [31:16] DRAM Refresh Time:      0 CSB clocks
 101  *      [15:8]  DRAM Command Time:      0 CSB clocks
 102  *      [07:00] DRAM Precharge Time:    0 CSB clocks
 103  * TIME_CFG1
 104  *      [31:26] DRAM tRFC:
 105  *      [25:21] DRAM tWR1:
 106  *      [20:17] DRAM tWRT1:
 107  *      [16:11] DRAM tDRR:
 108  *      [10:05] DRAM tRC:
 109  *      [04:00] DRAM tRAS:
 110  * TIME_CFG2
 111  *      [31:28] DRAM tRCD:
 112  *      [27:23] DRAM tFAW:
 113  *      [22:19] DRAM tRTW1:
 114  *      [18:15] DRAM tCCD:
 115  *      [14:10] DRAM tRTP:
 116  *      [09:05] DRAM tRP:
 117  *      [04:00] DRAM tRPA
 118  */
 119 #define CONFIG_SYS_MDDRC_SYS_CFG         0xEA804A00
 120 #define CONFIG_SYS_MDDRC_TIME_CFG0       0x06183D2E
 121 #define CONFIG_SYS_MDDRC_TIME_CFG1       0x68EC1168
 122 #define CONFIG_SYS_MDDRC_TIME_CFG2       0x34310864
 123
 124 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
 125 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
 126 #define CONFIG_SYS_DDRCMD_EM2           0x01020000
 127 #define CONFIG_SYS_DDRCMD_EM3           0x01030000
 128 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010000
 129 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
 130 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
 131 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   0x01010780
 132
 133 /* DDR Priority Manager Configuration */
 134 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 135 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 136 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 137 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 138 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 139 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 140 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 141 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 142 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 143 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 144 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 145 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 146 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 147 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 148 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 149 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 150 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 151 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 152 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 153 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 154 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 155 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 156 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 157
 158 /*
 159  * NOR FLASH on the Local Bus
 160  */
 161 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 162 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 163
 164 #define CONFIG_SYS_FLASH_BASE           0xFFC00000      /* start of FLASH */
 165 #define CONFIG_SYS_FLASH_SIZE           0x00400000      /* max flash size */
 166
 167 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 168 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 169 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 170 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
 171
 172 #undef CONFIG_SYS_FLASH_CHECKSUM
 173
 174 /*
 175  * NAND FLASH
 176  * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
 177  */
 178 #define CONFIG_CMD_NAND
 179 #define CONFIG_NAND_MPC5121_NFC
 180 #define CONFIG_SYS_NAND_BASE            0x40000000
 181 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 182
 183 /*
 184  * Configuration parameters for MPC5121 NAND driver
 185  */
 186 #define CONFIG_FSL_NFC_WIDTH            1
 187 #define CONFIG_FSL_NFC_WRITE_SIZE       2048
 188 #define CONFIG_FSL_NFC_SPARE_SIZE       64
 189 #define CONFIG_FSL_NFC_CHIPS            1
 190
 191 #define CONFIG_SYS_SRAM_BASE            0x30000000
 192 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 193
 194 /* ALE active low, data size 4bytes */
 195 #define CONFIG_SYS_CS0_CFG              0x05051150
 196
 197 /* Use not alternative CS timing */
 198 #define CONFIG_SYS_CS_ALETIMING         0x00000000
 199
 200 /* ALE active low, data size 4bytes */
 201 #define CONFIG_SYS_CS1_CFG              0x1f1f3090
 202 #define CONFIG_SYS_VPC3_BASE            0x82000000      /* start of VPC3 space */
 203 #define CONFIG_SYS_VPC3_SIZE            0x00010000      /* max VPC3 size */
 204
 205 /* Use SRAM for initial stack */
 206 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE /* Init RAM addr */
 207 #define CONFIG_SYS_INIT_RAM_SIZE                CONFIG_SYS_SRAM_SIZE
 208
 209 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 210 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 211
 212 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* Start of monitor */
 213 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Monitor length */
 214 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024) /* Malloc size */
 215
 216 /*
 217  * Serial Port
 218  */
 219 #define CONFIG_CONS_INDEX     1
 220
 221 /*
 222  * Serial console configuration
 223  */
 224 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
 225 #if CONFIG_PSC_CONSOLE != 3
 226 #error CONFIG_PSC_CONSOLE must be 3
 227 #endif
 228 #define CONFIG_BAUDRATE         9600    /* ... at 9600 bps */
 229 #define CONFIG_SYS_BAUDRATE_TABLE  \
 230         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 231
 232 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC3_TX_SIZE
 233 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC3_TX_ADDR
 234 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC3_RX_SIZE
 235 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC3_RX_ADDR
 236
 237 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 238 /* Use the HUSH parser */
 239 #define CONFIG_SYS_HUSH_PARSER
 240 #ifdef  CONFIG_SYS_HUSH_PARSER
 241 #endif
 242
 243 /* I2C */
 244 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 245 #undef CONFIG_SOFT_I2C                  /* so disable bit-banged I2C */
 246 #define CONFIG_I2C_MULTI_BUS
 247 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed */
 248 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* slave address */
 249
 250 /*
 251  * IIM - IC Identification Module
 252  */
 253 #undef CONFIG_IIM
 254
 255 /*
 256  * EEPROM configuration
 257  */
 258 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* 16-bit EEPROM address */
 259 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* Atmel: AT24C32A-10TQ-2.7 */
 260 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10        /* 10ms of delay */
 261 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5     /* 32-Byte Page Write Mode */
 262 #define CONFIG_SYS_EEPROM_WREN                  /* Use EEPROM write protect */
 263
 264 /*
 265  * Ethernet configuration
 266  */
 267 #define CONFIG_MPC512x_FEC      1
 268 #define CONFIG_PHY_ADDR         0x1
 269 #define CONFIG_MII              1       /* MII PHY management           */
 270 #define CONFIG_FEC_AN_TIMEOUT   1
 271 #define CONFIG_HAS_ETH0
 272
 273 /*
 274  * Configure on-board RTC
 275  */
 276 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 277 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 278 #define CONFIG_RTC_RX8025
 279
 280 /*
 281  * Environment
 282  */
 283 #define CONFIG_ENV_IS_IN_EEPROM         /* Store env in I2C EEPROM      */
 284 #define CONFIG_ENV_SIZE         0x1000
 285 #define CONFIG_ENV_OFFSET       0x0000  /* environment starts here      */
 286
 287 #define CONFIG_LOADS_ECHO               /* echo on for serial download  */
 288 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change        */
 289
 290 #include <config_cmd_default.h>
 291
 292 #define CONFIG_CMD_ASKENV
 293 #define CONFIG_CMD_DHCP
 294 #define CONFIG_CMD_I2C
 295 #define CONFIG_CMD_MII
 296 #define CONFIG_CMD_NFS
 297 #define CONFIG_CMD_PING
 298 #define CONFIG_CMD_REGINFO
 299 #define CONFIG_CMD_EEPROM
 300 #define CONFIG_CMD_DATE
 301 #undef CONFIG_CMD_FUSE
 302 #undef CONFIG_CMD_IDE
 303 #undef CONFIG_CMD_EXT2
 304 #define CONFIG_CMD_FAT
 305 #define CONFIG_CMD_JFFS2
 306 #define CONFIG_CMD_ELF
 307 #define CONFIG_DOS_PARTITION
 308
 309 /*
 310  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
 311  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
 312  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
 313  * to chapter 36 of the MPC5121e Reference Manual.
 314  */
 315 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
 316 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
 317
 318  /*
 319  * Miscellaneous configurable options
 320  */
 321 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 322 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 323 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 324
 325 #ifdef CONFIG_CMD_KGDB
 326 # define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
 327 #else
 328 # define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
 329 #endif
 330
 331 /* Print Buffer Size */
 332 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 333                                  sizeof(CONFIG_SYS_PROMPT) + 16)
 334 /* max number of command args */
 335 #define CONFIG_SYS_MAXARGS      32
 336 /* Boot Argument Buffer Size */
 337 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 338
 339 #define CONFIG_SYS_HZ           1000
 340
 341 /*
 342  * For booting Linux, the board info and command line data
 343  * have to be in the first 256 MB of memory, since this is
 344  * the maximum mapped by the Linux kernel during initialization.
 345  */
 346 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Linux initial memory map */
 347
 348 /* Cache Configuration */
 349 #define CONFIG_SYS_DCACHE_SIZE          32768
 350 #define CONFIG_SYS_CACHELINE_SIZE       32
 351 #ifdef CONFIG_CMD_KGDB
 352 #define CONFIG_SYS_CACHELINE_SHIFT      5
 353 #endif
 354
 355 #define CONFIG_SYS_HID0_INIT    0x000000000
 356 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_MACHINE_CHECK
 357 #define CONFIG_SYS_HID2         HID2_HBE
 358
 359 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 360
 361 #ifdef CONFIG_CMD_KGDB
 362 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 363 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 364 #endif
 365
 366 /*
 367  * Environment Configuration
 368  */
 369 #define CONFIG_TIMESTAMP
 370
 371 #define CONFIG_HOSTNAME         mecp512x
 372 #define CONFIG_BOOTFILE         "/tftpboot/mecp512x/uImage"
 373 #define CONFIG_ROOTPATH         "/tftpboot/mecp512x/target_root"
 374
 375 #define CONFIG_LOADADDR         400000  /* def. location for tftp and bootm */
 376
 377 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 378 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs*/
 379
 380 #define CONFIG_PREBOOT  "echo;" \
 381         "echo Welcome to MECP5123" \
 382         "echo"
 383
 384 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 385         "u-boot_addr_r=200000\0"                                        \
 386         "kernel_addr_r=600000\0"                                        \
 387         "fdt_addr_r=880000\0"                                           \
 388         "ramdisk_addr_r=900000\0"                                       \
 389         "u-boot_addr=FFF00000\0"                                        \
 390         "kernel_addr=FFC40000\0"                                        \
 391         "fdt_addr=FFEC0000\0"                                           \
 392         "ramdisk_addr=FC040000\0"                                       \
 393         "ramdiskfile=/tftpboot/mecp512x/uRamdisk\0"                     \
 394         "u-boot=/tftpboot/mecp512x/u-boot.bin\0"                        \
 395         "bootfile=/tftpboot/mecp512x/uImage\0"                          \
 396         "fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0"                     \
 397         "rootpath=/tftpboot/mecp512x/target_root\n"                     \
 398         "netdev=eth0\0"                                                 \
 399         "consdev=ttyPSC0\0"                                             \
 400         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 401                 "nfsroot=${serverip}:${rootpath}\0"                     \
 402         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 403         "addip=setenv bootargs ${bootargs} "                            \
 404                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 405                 ":${hostname}:${netdev}:off panic=1\0"                  \
 406         "addtty=setenv bootargs ${bootargs} "                           \
 407                 "console=${consdev},${baudrate}\0"                      \
 408         "flash_nfs=run nfsargs addip addtty;"                           \
 409                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 410         "flash_self=run ramargs addip addtty;"                          \
 411                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 412         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 413                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 414                 "run nfsargs addip addtty;"                             \
 415                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 416         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
 417                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
 418                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 419                 "run ramargs addip addtty;"                             \
 420                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 421         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 422         "update=protect off ${u-boot_addr} +${filesize};"               \
 423                 "era ${u-boot_addr} +${filesize};"                      \
 424                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
 425         "upd=run load update\0"                                         \
 426         ""
 427
 428 #define CONFIG_BOOTCOMMAND      "run flash_self"
 429
 430 #define CONFIG_OF_LIBFDT
 431 #define CONFIG_OF_BOARD_SETUP
 432
 433 #define OF_CPU                  "PowerPC,5121@0"
 434 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 435 #define OF_TBCLK                (bd->bi_busfreq / 4)
 436 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
 437
 438 #endif  /* __CONFIG_H */