2 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _CONFIG_DB_MV7846MP_GP_H
8 #define _CONFIG_DB_MV7846MP_GP_H
11 * High Level Configuration Options (easy to change)
13 #define CONFIG_DISPLAY_BOARDINFO_LATE
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
20 #define CONFIG_SYS_TEXT_BASE 0x00800000
21 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
24 * Commands configuration
26 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
27 #define CONFIG_CMD_ENV
30 #define CONFIG_SYS_I2C
31 #define CONFIG_SYS_I2C_MVTWSI
32 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
33 #define CONFIG_SYS_I2C_SLAVE 0x0
34 #define CONFIG_SYS_I2C_SPEED 100000
36 /* SPI NOR flash default params, used by sf commands */
37 #define CONFIG_SF_DEFAULT_SPEED 1000000
38 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
40 /* Environment in SPI NOR flash */
41 #define CONFIG_ENV_IS_IN_SPI_FLASH
42 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
43 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
44 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
46 #define CONFIG_PHY_MARVELL /* there is a marvell phy */
47 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
49 #define CONFIG_SYS_ALT_MEMTEST
52 * mv-common.h should be defined after CMD configs since it used them
53 * to enable certain macros
55 #include "mv-common.h"
58 * Memory layout while starting into the bin_hdr via the
61 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
62 * 0x4000.4030 bin_hdr start address
63 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
64 * 0x4007.fffc BootROM stack top
66 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
67 * L2 cache thus cannot be used.
72 #define CONFIG_SPL_FRAMEWORK
73 #define CONFIG_SPL_TEXT_BASE 0x40004030
74 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
76 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
77 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
79 #ifdef CONFIG_SPL_BUILD
80 #define CONFIG_SYS_MALLOC_SIMPLE
83 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
84 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
86 /* SPL related SPI defines */
87 #define CONFIG_SPL_SPI_LOAD
88 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
90 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
91 #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
92 #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
94 #endif /* _CONFIG_DB_MV7846MP_GP_H */