1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
6 #ifndef _CONFIG_DB_MV7846MP_GP_H
7 #define _CONFIG_DB_MV7846MP_GP_H
10 * High Level Configuration Options (easy to change)
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
18 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
21 * Commands configuration
25 #define CONFIG_SYS_I2C
26 #define CONFIG_SYS_I2C_MVTWSI
27 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
28 #define CONFIG_SYS_I2C_SLAVE 0x0
29 #define CONFIG_SYS_I2C_SPEED 100000
31 /* SPI NOR flash default params, used by sf commands */
33 /* Environment in SPI NOR flash */
35 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
38 * mv-common.h should be defined after CMD configs since it used them
39 * to enable certain macros
41 #include "mv-common.h"
44 * Memory layout while starting into the bin_hdr via the
47 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
48 * 0x4000.4030 bin_hdr start address
49 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
50 * 0x4007.fffc BootROM stack top
52 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
53 * L2 cache thus cannot be used.
58 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
60 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
61 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
63 #ifdef CONFIG_SPL_BUILD
64 #define CONFIG_SYS_MALLOC_SIMPLE
67 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
68 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
70 /* SPL related SPI defines */
72 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
73 #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
74 #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
76 #endif /* _CONFIG_DB_MV7846MP_GP_H */