1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Menlosystems M53Menlo configuration
5 * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
9 #ifndef __M53MENLO_CONFIG_H__
10 #define __M53MENLO_CONFIG_H__
12 #include <asm/arch/imx-regs.h>
14 #define CONFIG_REVISION_TAG
15 #define CONFIG_SYS_FSL_CLK
17 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
20 * Memory configurations
22 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
23 #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
24 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
25 #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
26 #define PHYS_SDRAM_SIZE (gd->ram_size)
27 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
29 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
30 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
31 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
33 #define CONFIG_SYS_INIT_SP_OFFSET \
34 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
35 #define CONFIG_SYS_INIT_SP_ADDR \
36 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
39 * U-Boot general configurations
41 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
42 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
43 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
44 /* Boot argument buffer size */
49 #define CONFIG_MXC_UART
50 #define CONFIG_MXC_UART_BASE UART1_BASE
56 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
57 #define CONFIG_SYS_FSL_ESDHC_NUM 1
63 #ifdef CONFIG_CMD_NAND
64 #define CONFIG_SYS_MAX_NAND_DEVICE 1
65 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
66 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
67 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
68 #define CONFIG_SYS_NAND_LARGEPAGE
69 #define CONFIG_MXC_NAND_HWECC
71 /* Environment is in NAND */
72 #define CONFIG_ENV_RANGE (0x00080000) /* 512 KiB */
76 * Ethernet on SOC (FEC)
79 #define CONFIG_FEC_MXC
80 #define IMX_FEC_BASE FEC_BASE_ADDR
81 #define CONFIG_FEC_MXC_PHYADDR 0x0
83 #define CONFIG_DISCOVER_PHY
84 #define CONFIG_FEC_XCV_TYPE RMII
85 #define CONFIG_ETHPRIME "FEC0"
92 #define CONFIG_SYS_I2C
93 #define CONFIG_SYS_I2C_MXC
94 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
95 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
96 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
97 #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
103 #ifdef CONFIG_CMD_DATE
104 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
105 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
111 #ifdef CONFIG_CMD_USB
112 #define CONFIG_MXC_USB_PORT 1
113 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
114 #define CONFIG_MXC_USB_FLAGS 0
120 #ifdef CONFIG_CMD_SATA
121 #define CONFIG_SYS_SATA_MAX_DEVICE 1
122 #define CONFIG_DWC_AHSATA_PORT_ID 0
123 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
130 #define CONFIG_VIDEO_BMP_RLE8
131 #define CONFIG_VIDEO_BMP_GZIP
132 #define CONFIG_SPLASH_SCREEN
133 #define CONFIG_SPLASHIMAGE_GUARD
134 #define CONFIG_SPLASH_SCREEN_ALIGN
135 #define CONFIG_BMP_16BPP
136 #define CONFIG_VIDEO_LOGO
137 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
140 #define CONFIG_SYS_LDB_CLOCK 33260000
141 #define CONFIG_IMX_VIDEO_SKIP
142 #define CONFIG_SPLASH_SOURCE
145 #define CONFIG_FSL_IIM
152 #define CONFIG_CMDLINE_TAG
153 #define CONFIG_INITRD_TAG
154 #define CONFIG_REVISION_TAG
155 #define CONFIG_SETUP_MEMORY_TAGS
156 #define CONFIG_BOOTFILE "boot/fitImage"
157 #define CONFIG_LOADADDR 0x70800000
158 #define CONFIG_BOOTCOMMAND "run mmc_mmc"
159 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
164 #define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
165 #define CONFIG_SPL_PAD_TO 0x8000
166 #define CONFIG_SPL_STACK 0x70004000
168 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
169 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
170 #define CONFIG_SYS_NAND_OOBSIZE 64
171 #define CONFIG_SYS_NAND_PAGE_COUNT 64
172 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
173 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
178 #define CONFIG_HOSTNAME "m53menlo"
180 #define CONFIG_EXTRA_ENV_SETTINGS \
181 "consdev=ttymxc0\0" \
182 "baudrate=115200\0" \
183 "bootscript=boot.scr\0" \
187 "kernel_addr_r=0x72000000\0" \
188 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
189 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
191 "splashsource=mmc_fs\0" \
192 "splashfile=boot/usplash.bmp.gz\0" \
193 "splashimage=0x88000000\0" \
195 "stdout=serial,vidconsole\0" \
196 "stderr=serial,vidconsole\0" \
198 "setenv bootargs ${bootargs} " \
199 "console=${consdev},${baudrate}\0" \
201 "setenv bootargs ${bootargs} " \
202 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
203 ":${hostname}:${netdev}:off\0" \
204 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
206 "setenv bootargs ${bootargs} ${miscargs}\0" \
207 "addargs=run addcons addmisc addmtd\0" \
209 "mmc rescan ; load mmc ${mmcdev}:${mmcpart} " \
210 "${kernel_addr_r} ${bootfile}\0" \
211 "miscargs=nohlt panic=1\0" \
212 "mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \
215 "run mmcload mmcargs addargs ; " \
216 "bootm ${kernel_addr_r}\0" \
217 "netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
219 "run netload nfsargs addip addargs ; " \
220 "bootm ${kernel_addr_r}\0" \
222 "setenv bootargs root=/dev/nfs rw " \
223 "nfsroot=${serverip}:${rootpath}${hostname},v3,tcp\0" \
226 "if test -e mmc 0:1 ${bootscript} ; then " \
227 "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
229 "echo Running bootscript... ; " \
230 "source ${kernel_addr_r} ; " \
234 #if defined(CONFIG_SPL_BUILD)
235 #undef CONFIG_WATCHDOG
236 #define CONFIG_HW_WATCHDOG
239 #endif /* __M53MENLO_CONFIG_H__ */