include/configs/lx2160ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #ifndef __LX2_RDB_H
   7 #define __LX2_RDB_H
   8
   9 #include "lx2160a_common.h"
  10
  11 /* Qixis */
  12 #define QIXIS_XMAP_MASK                 0x07
  13 #define QIXIS_XMAP_SHIFT                5
  14 #define QIXIS_RST_CTL_RESET_EN          0x30
  15 #define QIXIS_LBMAP_DFLTBANK            0x00
  16 #define QIXIS_LBMAP_ALTBANK             0x20
  17 #define QIXIS_LBMAP_QSPI                0x00
  18 #define QIXIS_RCW_SRC_QSPI              0xff
  19 #define QIXIS_RST_CTL_RESET             0x31
  20 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
  21 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
  22 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
  23 #define QIXIS_LBMAP_MASK                0x0f
  24 #define QIXIS_LBMAP_SD
  25 #define QIXIS_RCW_SRC_SD           0x08
  26 #define NON_EXTENDED_DUTCFG
  27
  28 /* VID */
  29
  30 #define I2C_MUX_CH_VOL_MONITOR          0xA
  31 /* Voltage monitor on channel 2*/
  32 #define I2C_VOL_MONITOR_ADDR            0x63
  33 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
  34 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
  35 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
  36 #define CONFIG_VID_FLS_ENV              "lx2160ardb_vdd_mv"
  37 #define CONFIG_VID
  38
  39 /* The lowest and highest voltage allowed*/
  40 #define VDD_MV_MIN                      775
  41 #define VDD_MV_MAX                      855
  42
  43 /* PM Bus commands code for LTC3882*/
  44 #define PMBUS_CMD_PAGE                  0x0
  45 #define PMBUS_CMD_READ_VOUT             0x8B
  46 #define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
  47 #define PMBUS_CMD_VOUT_COMMAND          0x21
  48 #define PWM_CHANNEL0                    0x0
  49
  50 #define CONFIG_VOL_MONITOR_LTC3882_SET
  51 #define CONFIG_VOL_MONITOR_LTC3882_READ
  52
  53 /* RTC */
  54 #define CONFIG_SYS_RTC_BUS_NUM          4
  55
  56 /* MAC/PHY configuration */
  57 #if defined(CONFIG_FSL_MC_ENET)
  58 #define CONFIG_MII
  59 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
  60
  61 #define AQR107_PHY_ADDR1        0x04
  62 #define AQR107_PHY_ADDR2        0x05
  63
  64 #define CORTINA_NO_FW_UPLOAD
  65 #define CORTINA_PHY_ADDR1       0x0
  66 #define INPHI_PHY_ADDR1         0x0
  67
  68 #define RGMII_PHY_ADDR1         0x01
  69 #define RGMII_PHY_ADDR2         0x02
  70
  71 #endif
  72
  73 /* EEPROM */
  74 #define CONFIG_ID_EEPROM
  75 #define CONFIG_SYS_I2C_EEPROM_NXID
  76 #define CONFIG_SYS_EEPROM_BUS_NUM                  0
  77 #define CONFIG_SYS_I2C_EEPROM_ADDR                 0x57
  78 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN      1
  79 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     3
  80 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  81
  82 /* Initial environment variables */
  83 #define CONFIG_EXTRA_ENV_SETTINGS               \
  84         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
  85         "scriptaddr=0x80800000\0"               \
  86         "kernel_addr_r=0x81000000\0"            \
  87         "pxefile_addr_r=0x81000000\0"           \
  88         "fdt_addr_r=0x88000000\0"               \
  89         "ramdisk_addr_r=0x89000000\0"           \
  90         "loadaddr=0x80100000\0"                 \
  91         "kernel_addr=0x100000\0"                \
  92         "ramdisk_addr=0x800000\0"               \
  93         "ramdisk_size=0x2000000\0"              \
  94         "fdt_high=0xa0000000\0"                 \
  95         "initrd_high=0xffffffffffffffff\0"      \
  96         "kernel_start=0x21000000\0"             \
  97         "lx2160ardb_vdd_mv=800\0"               \
  98         "mcmemsize=0x40000000\0"
  99
 100 #include <asm/fsl_secure_boot.h>
 101
 102 #endif /* __LX2_RDB_H */