include/configs/lx2160a_common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #ifndef __LX2_COMMON_H
   7 #define __LX2_COMMON_H
   8
   9 #include <asm/arch/stream_id_lsch3.h>
  10 #include <asm/arch/config.h>
  11 #include <asm/arch/soc.h>
  12
  13 #define CONFIG_REMAKE_ELF
  14 #define CONFIG_FSL_LAYERSCAPE
  15 #define CONFIG_GICV3
  16 #define CONFIG_FSL_TZPC_BP147
  17 #define CONFIG_FSL_MEMAC
  18
  19 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SYS_TEXT_BASE
  20 #define CONFIG_SYS_FLASH_BASE           0x20000000
  21
  22 #define CONFIG_SKIP_LOWLEVEL_INIT
  23 #define CONFIG_BOARD_EARLY_INIT_F       1
  24
  25 /* DDR */
  26 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  27 #define CONFIG_SYS_FSL_DDR_INTLV_256B   /* force 256 byte interleaving */
  28 #define CONFIG_VERY_BIG_RAM
  29 #define CONFIG_SYS_DDR_SDRAM_BASE               0x80000000UL
  30 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  31 #define CONFIG_SYS_DDR_BLOCK2_BASE              0x2080000000ULL
  32 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       2
  33 #define CONFIG_SYS_SDRAM_SIZE                   0x200000000UL
  34 #define CONFIG_DDR_SPD
  35 #define CONFIG_DDR_ECC
  36 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  37 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  38 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  39 #define SPD_EEPROM_ADDRESS1             0x51
  40 #define SPD_EEPROM_ADDRESS2             0x52
  41 #define SPD_EEPROM_ADDRESS3             0x53
  42 #define SPD_EEPROM_ADDRESS4             0x54
  43 #define SPD_EEPROM_ADDRESS5             0x55
  44 #define SPD_EEPROM_ADDRESS6             0x56
  45 #define SPD_EEPROM_ADDRESS              SPD_EEPROM_ADDRESS1
  46 #define CONFIG_SYS_SPD_BUS_NUM          0       /* SPD on I2C bus 0 */
  47 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  48 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  49 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
  50 #define CONFIG_SYS_MONITOR_LEN          (936 * 1024)
  51
  52 /* Miscellaneous configurable options */
  53 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
  54
  55 /* SMP Definitinos  */
  56 #define CPU_RELEASE_ADDR                secondary_boot_func
  57
  58 /* Generic Timer Definitions */
  59 /*
  60  * This is not an accurate number. It is used in start.S. The frequency
  61  * will be udpated later when get_bus_freq(0) is available.
  62  */
  63
  64 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  65
  66 /* Size of malloc() pool */
  67 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 2048 * 1024)
  68
  69 /* Serial Port */
  70 #define CONFIG_PL01X_SERIAL
  71 #define CONFIG_PL011_CLOCK              (get_bus_freq(0) / 4)
  72 #define CONFIG_SYS_SERIAL0              0x21c0000
  73 #define CONFIG_SYS_SERIAL1              0x21d0000
  74 #define CONFIG_SYS_SERIAL2              0x21e0000
  75 #define CONFIG_SYS_SERIAL3              0x21f0000
  76 /*below might needs to be removed*/
  77 #define CONFIG_PL01x_PORTS              {(void *)CONFIG_SYS_SERIAL0, \
  78                                         (void *)CONFIG_SYS_SERIAL1, \
  79                                         (void *)CONFIG_SYS_SERIAL2, \
  80                                         (void *)CONFIG_SYS_SERIAL3 }
  81 #define CONFIG_BAUDRATE                 115200
  82 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  83
  84 /* MC firmware */
  85 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH         0x20000
  86 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET        0x00F00000
  87 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH         0x20000
  88 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET        0x00F20000
  89 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS        5000
  90
  91 /* Define phy_reset function to boot the MC based on mcinitcmd.
  92  * This happens late enough to properly fixup u-boot env MAC addresses.
  93  */
  94 #define CONFIG_RESET_PHY_R
  95
  96 /*
  97  * Carve out a DDR region which will not be used by u-boot/Linux
  98  *
  99  * It will be used by MC and Debug Server. The MC region must be
 100  * 512MB aligned, so the min size to hide is 512MB.
 101  */
 102 #ifdef CONFIG_FSL_MC_ENET
 103 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE    (512UL * 1024 * 1024)
 104 #endif
 105
 106 /* I2C bus multiplexer */
 107 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 108 #define I2C_MUX_CH_DEFAULT              0x8
 109
 110 /* RTC */
 111 #define RTC
 112 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 113
 114 /* EEPROM */
 115 #define CONFIG_ID_EEPROM
 116 #define CONFIG_SYS_I2C_EEPROM_NXID
 117 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 118 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 119 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 120 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 121 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 122
 123 /* Qixis */
 124 #define CONFIG_FSL_QIXIS
 125 #define CONFIG_QIXIS_I2C_ACCESS
 126 #define CONFIG_SYS_I2C_FPGA_ADDR                0x66
 127
 128 /* PCI */
 129 #ifdef CONFIG_PCI
 130 #define CONFIG_SYS_PCI_64BIT
 131 #define CONFIG_PCI_SCAN_SHOW
 132 #endif
 133
 134 /* MMC */
 135 #ifdef CONFIG_MMC
 136 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 137 #endif
 138
 139 /* SATA */
 140
 141 #ifdef CONFIG_SCSI
 142 #define CONFIG_SCSI_AHCI_PLAT
 143 #define CONFIG_SYS_SATA1                AHCI_BASE_ADDR1
 144 #define CONFIG_SYS_SATA2                AHCI_BASE_ADDR2
 145 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     1
 146 #define CONFIG_SYS_SCSI_MAX_LUN         1
 147 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 148                                         CONFIG_SYS_SCSI_MAX_LUN)
 149 #endif
 150
 151 /* USB */
 152 #ifdef CONFIG_USB
 153 #define CONFIG_HAS_FSL_XHCI_USB
 154 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 155 #endif
 156
 157 /* FlexSPI */
 158 #ifdef CONFIG_NXP_FSPI
 159 #define NXP_FSPI_FLASH_SIZE             SZ_64M
 160 #define NXP_FSPI_FLASH_NUM              1
 161 #endif
 162
 163 #ifndef __ASSEMBLY__
 164 unsigned long get_board_sys_clk(void);
 165 unsigned long get_board_ddr_clk(void);
 166 #endif
 167
 168 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
 169 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
 170 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ / 4)
 171
 172 #define CONFIG_HWCONFIG
 173 #define HWCONFIG_BUFFER_SIZE            128
 174
 175 #define CONFIG_SYS_MMC_ENV_DEV          0
 176 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 177 #define CONFIG_ENV_SECT_SIZE            0x20000
 178 #define CONFIG_ENV_OFFSET               0x500000
 179 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + \
 180                                          CONFIG_ENV_OFFSET)
 181
 182 /* Allow to overwrite serial and ethaddr */
 183 #define CONFIG_ENV_OVERWRITE
 184
 185 /* Monitor Command Prompt */
 186 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 187 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 188                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 189 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 190 #define CONFIG_CMDLINE_EDITING          1
 191 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 192
 193 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 194
 195 /* Initial environment variables */
 196 #define XSPI_NOR_BOOTCOMMAND    "fsl_mc apply dpl 0x20d00000;" \
 197                                 "sf probe 0:0;" \
 198                                 "sf read 0xa0000000 0x1000000 0x3000000;" \
 199                                 "bootm 0xa0000000"
 200
 201 #define SD_BOOTCOMMAND          "mmc read 0xa0000000 0x6800 0xA0;" \
 202                                 "fsl_mc apply dpl 0xa0000000;" \
 203                                 "mmc read 0xb0000000 0x8000 0x1d000;" \
 204                                 "bootm 0xb0000000"
 205
 206 #define XSPI_MC_INIT_CMD                        \
 207         "fsl_mc start mc 0x20a00000 0x20e00000\0"
 208
 209 #define SD_MC_INIT_CMD                          \
 210         "mmc read 0x80000000 0x5000 0x800;"     \
 211         "mmc read 0x80100000 0x7000 0x800;"     \
 212         "fsl_mc start mc 0x80000000 0x80100000\0"
 213
 214 #endif /* __LX2_COMMON_H */