2 * Copyright (C) 2014 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_SYS_GENERIC_BOARD
12 #define CONFIG_REMAKE_ELF
13 #define CONFIG_FSL_LSCH3
14 #define CONFIG_LS2085A
16 #define CONFIG_FSL_TZPC_BP147
19 #define CONFIG_ARM_ERRATA_828024
20 #define CONFIG_ARM_ERRATA_826974
22 #include <asm/arch-fsl-lsch3/config.h>
23 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
24 #define CONFIG_SYS_HAS_SERDES
27 /* We need architecture specific misc initializations */
28 #define CONFIG_ARCH_MISC_INIT
30 /* Link Definitions */
32 #define CONFIG_SYS_TEXT_BASE 0x80400000
34 #define CONFIG_SYS_TEXT_BASE 0x30100000
38 #define CONFIG_SYS_NO_FLASH
41 #define CONFIG_SUPPORT_RAW_INITRD
43 #define CONFIG_SKIP_LOWLEVEL_INIT
44 #define CONFIG_BOARD_EARLY_INIT_F 1
46 /* Flat Device Tree Definitions */
47 #define CONFIG_OF_LIBFDT
48 #define CONFIG_OF_BOARD_SETUP
50 /* new uImage format support */
52 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
55 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
57 #ifndef CONFIG_SYS_FSL_DDR4
58 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
59 #define CONFIG_SYS_DDR_RAW_TIMING
62 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
64 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
65 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
66 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
67 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
68 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
73 #define CPU_RELEASE_ADDR secondary_boot_func
75 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
76 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
78 * DDR controller use 0 as the base address for binding.
79 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
81 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
82 #define CONFIG_DP_DDR_CTRL 2
83 #define CONFIG_DP_DDR_NUM_CTRLS 1
85 /* Generic Timer Definitions */
87 * This is not an accurate number. It is used in start.S. The frequency
88 * will be udpated later when get_bus_freq(0) is available.
90 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
92 /* Size of malloc() pool */
93 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
96 #define CONFIG_CMD_I2C
97 #define CONFIG_SYS_I2C
98 #define CONFIG_SYS_I2C_MXC
99 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
100 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
103 #define CONFIG_CONS_INDEX 1
104 #define CONFIG_SYS_NS16550
105 #define CONFIG_SYS_NS16550_SERIAL
106 #define CONFIG_SYS_NS16550_REG_SIZE 1
107 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
109 #define CONFIG_BAUDRATE 115200
110 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
113 #define CONFIG_FSL_IFC
116 * During booting, IFC is mapped at the region of 0x30000000.
117 * But this region is limited to 256MB. To accommodate NOR, promjet
118 * and FPGA. This region is divided as below:
119 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
120 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
121 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
123 * To accommodate bigger NOR flash and other devices, we will map IFC
124 * chip selects to as below:
125 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
126 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
127 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
128 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
129 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
131 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
132 * CONFIG_SYS_FLASH_BASE has the final address (core view)
133 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
134 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
135 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
138 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
139 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
140 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
142 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
143 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
145 #ifndef CONFIG_SYS_NO_FLASH
146 #define CONFIG_FLASH_CFI_DRIVER
147 #define CONFIG_SYS_FLASH_CFI
148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
149 #define CONFIG_SYS_FLASH_QUIET_TEST
153 unsigned long long get_qixis_addr(void);
155 #define QIXIS_BASE get_qixis_addr()
156 #define QIXIS_BASE_PHYS 0x20000000
157 #define QIXIS_BASE_PHYS_EARLY 0xC000000
158 #define QIXIS_STAT_PRES1 0xb
159 #define QIXIS_SDID_MASK 0x07
160 #define QIXIS_ESDHC_NO_ADAPTER 0x7
162 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
163 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
165 /* Debug Server firmware */
166 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
168 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
171 #define CONFIG_FSL_MC_ENET
172 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
173 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
174 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
175 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
176 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
177 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
179 /* Carve out a DDR region which will not be used by u-boot/Linux */
180 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
181 #define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide()
185 #define CONFIG_PCIE1 /* PCIE controler 1 */
186 #define CONFIG_PCIE2 /* PCIE controler 2 */
187 #define CONFIG_PCIE3 /* PCIE controler 3 */
188 #define CONFIG_PCIE4 /* PCIE controler 4 */
189 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
190 #define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
192 #define CONFIG_SYS_PCI_64BIT
194 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
195 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
196 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
197 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
199 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
200 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
201 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
203 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
204 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
205 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
207 /* Command line configuration */
208 #define CONFIG_CMD_CACHE
209 #define CONFIG_CMD_DHCP
210 #define CONFIG_CMD_ENV
211 #define CONFIG_CMD_MII
212 #define CONFIG_CMD_PING
214 /* Miscellaneous configurable options */
215 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
216 #define CONFIG_ARCH_EARLY_INIT_R
218 /* Physical Memory Map */
219 /* fixme: these need to be checked against the board */
220 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
222 #define CONFIG_NR_DRAM_BANKS 3
224 #define CONFIG_HWCONFIG
225 #define HWCONFIG_BUFFER_SIZE 128
227 #define CONFIG_DISPLAY_CPUINFO
229 /* Initial environment variables */
230 #define CONFIG_EXTRA_ENV_SETTINGS \
231 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
232 "loadaddr=0x80100000\0" \
233 "kernel_addr=0x100000\0" \
234 "ramdisk_addr=0x800000\0" \
235 "ramdisk_size=0x2000000\0" \
236 "fdt_high=0xa0000000\0" \
237 "initrd_high=0xffffffffffffffff\0" \
238 "kernel_start=0x581200000\0" \
239 "kernel_load=0xa0000000\0" \
240 "kernel_size=0x2000000\0" \
241 "console=ttyAMA0,38400n8\0"
243 #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
244 "earlycon=uart8250,mmio,0x21c0600,115200 " \
245 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
246 " hugepagesz=2m hugepages=16"
247 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
248 "$kernel_size && bootm $kernel_load"
249 #define CONFIG_BOOTDELAY 10
251 /* Monitor Command Prompt */
252 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
253 #define CONFIG_SYS_PROMPT "=> "
254 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
255 sizeof(CONFIG_SYS_PROMPT) + 16)
256 #define CONFIG_SYS_HUSH_PARSER
257 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
258 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
259 #define CONFIG_SYS_LONGHELP
260 #define CONFIG_CMDLINE_EDITING 1
261 #define CONFIG_AUTO_COMPLETE
262 #define CONFIG_SYS_MAXARGS 64 /* max command args */
265 unsigned long get_dram_size_to_hide(void);
268 #define CONFIG_PANIC_HANG /* do not reset board on panic */
270 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
271 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
272 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
273 #define CONFIG_SPL_ENV_SUPPORT
274 #define CONFIG_SPL_FRAMEWORK
275 #define CONFIG_SPL_I2C_SUPPORT
276 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
277 #define CONFIG_SPL_LIBCOMMON_SUPPORT
278 #define CONFIG_SPL_LIBGENERIC_SUPPORT
279 #define CONFIG_SPL_MAX_SIZE 0x16000
280 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
281 #define CONFIG_SPL_NAND_SUPPORT
282 #define CONFIG_SPL_SERIAL_SUPPORT
283 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
284 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
285 #define CONFIG_SPL_TEXT_BASE 0x1800a000
287 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
288 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
289 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
290 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
291 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
293 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
296 #endif /* __LS2_COMMON_H */