2 * Copyright (C) 2014 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
11 #define CONFIG_REMAKE_ELF
12 #define CONFIG_FSL_LSCH3
13 #define CONFIG_LS2085A
15 #define CONFIG_FSL_TZPC_BP147
18 #define CONFIG_ARM_ERRATA_828024
19 #define CONFIG_ARM_ERRATA_826974
21 #include <asm/arch-fsl-lsch3/ls2085a_stream_id.h>
22 #include <asm/arch-fsl-lsch3/config.h>
23 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
24 #define CONFIG_SYS_HAS_SERDES
27 /* We need architecture specific misc initializations */
28 #define CONFIG_ARCH_MISC_INIT
30 /* Link Definitions */
32 #define CONFIG_SYS_TEXT_BASE 0x80400000
34 #define CONFIG_SYS_TEXT_BASE 0x30100000
38 #define CONFIG_SYS_NO_FLASH
41 #define CONFIG_SUPPORT_RAW_INITRD
43 #define CONFIG_SKIP_LOWLEVEL_INIT
44 #define CONFIG_BOARD_EARLY_INIT_F 1
46 /* Flat Device Tree Definitions */
47 #define CONFIG_OF_LIBFDT
48 #define CONFIG_OF_BOARD_SETUP
50 /* new uImage format support */
52 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
55 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
57 #ifndef CONFIG_SYS_FSL_DDR4
58 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
59 #define CONFIG_SYS_DDR_RAW_TIMING
62 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
64 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
65 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
66 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
67 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
68 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
73 #define CPU_RELEASE_ADDR secondary_boot_func
75 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
76 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
78 * DDR controller use 0 as the base address for binding.
79 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
81 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
82 #define CONFIG_DP_DDR_CTRL 2
83 #define CONFIG_DP_DDR_NUM_CTRLS 1
85 /* Generic Timer Definitions */
87 * This is not an accurate number. It is used in start.S. The frequency
88 * will be udpated later when get_bus_freq(0) is available.
90 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
92 /* Size of malloc() pool */
93 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
96 #define CONFIG_CMD_I2C
97 #define CONFIG_SYS_I2C
98 #define CONFIG_SYS_I2C_MXC
99 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
100 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
101 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
102 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
105 #define CONFIG_CONS_INDEX 1
106 #define CONFIG_SYS_NS16550
107 #define CONFIG_SYS_NS16550_SERIAL
108 #define CONFIG_SYS_NS16550_REG_SIZE 1
109 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
111 #define CONFIG_BAUDRATE 115200
112 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
115 #define CONFIG_FSL_IFC
118 * During booting, IFC is mapped at the region of 0x30000000.
119 * But this region is limited to 256MB. To accommodate NOR, promjet
120 * and FPGA. This region is divided as below:
121 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
122 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
123 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
125 * To accommodate bigger NOR flash and other devices, we will map IFC
126 * chip selects to as below:
127 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
128 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
129 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
130 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
131 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
133 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
134 * CONFIG_SYS_FLASH_BASE has the final address (core view)
135 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
136 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
137 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
140 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
141 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
142 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
144 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
145 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
147 #ifndef CONFIG_SYS_NO_FLASH
148 #define CONFIG_FLASH_CFI_DRIVER
149 #define CONFIG_SYS_FLASH_CFI
150 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
151 #define CONFIG_SYS_FLASH_QUIET_TEST
155 unsigned long long get_qixis_addr(void);
157 #define QIXIS_BASE get_qixis_addr()
158 #define QIXIS_BASE_PHYS 0x20000000
159 #define QIXIS_BASE_PHYS_EARLY 0xC000000
160 #define QIXIS_STAT_PRES1 0xb
161 #define QIXIS_SDID_MASK 0x07
162 #define QIXIS_ESDHC_NO_ADAPTER 0x7
164 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
165 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
167 /* Debug Server firmware */
168 #define CONFIG_FSL_DEBUG_SERVER
170 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
173 #define CONFIG_FSL_MC_ENET
174 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
175 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
176 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
177 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
178 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
179 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
180 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
183 * Carve out a DDR region which will not be used by u-boot/Linux
185 * It will be used by MC and Debug Server. The MC region must be
186 * 512MB aligned, so the min size to hide is 512MB.
188 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
189 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
190 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
191 #define CONFIG_SYS_MEM_TOP_HIDE_MIN (512UL * 1024 * 1024)
192 #define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide()
196 #define CONFIG_PCIE1 /* PCIE controler 1 */
197 #define CONFIG_PCIE2 /* PCIE controler 2 */
198 #define CONFIG_PCIE3 /* PCIE controler 3 */
199 #define CONFIG_PCIE4 /* PCIE controler 4 */
200 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
201 #define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
203 #define CONFIG_SYS_PCI_64BIT
205 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
206 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
207 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
208 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
210 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
211 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
212 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
214 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
215 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
216 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
218 /* Command line configuration */
219 #define CONFIG_CMD_CACHE
220 #define CONFIG_CMD_DHCP
221 #define CONFIG_CMD_ENV
222 #define CONFIG_CMD_GREPENV
223 #define CONFIG_CMD_MII
224 #define CONFIG_CMD_PING
226 /* Miscellaneous configurable options */
227 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
228 #define CONFIG_ARCH_EARLY_INIT_R
230 /* Physical Memory Map */
231 /* fixme: these need to be checked against the board */
232 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
234 #define CONFIG_NR_DRAM_BANKS 3
236 #define CONFIG_HWCONFIG
237 #define HWCONFIG_BUFFER_SIZE 128
239 #define CONFIG_DISPLAY_CPUINFO
241 /* Initial environment variables */
242 #define CONFIG_EXTRA_ENV_SETTINGS \
243 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
244 "loadaddr=0x80100000\0" \
245 "kernel_addr=0x100000\0" \
246 "ramdisk_addr=0x800000\0" \
247 "ramdisk_size=0x2000000\0" \
248 "fdt_high=0xa0000000\0" \
249 "initrd_high=0xffffffffffffffff\0" \
250 "kernel_start=0x581200000\0" \
251 "kernel_load=0xa0000000\0" \
252 "kernel_size=0x2800000\0" \
253 "console=ttyAMA0,38400n8\0"
255 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
256 "earlycon=uart8250,mmio,0x21c0500,115200 " \
257 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
258 " hugepagesz=2m hugepages=16"
259 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
260 "$kernel_size && bootm $kernel_load"
261 #define CONFIG_BOOTDELAY 10
263 /* Monitor Command Prompt */
264 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
265 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
266 sizeof(CONFIG_SYS_PROMPT) + 16)
267 #define CONFIG_SYS_HUSH_PARSER
268 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
269 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
270 #define CONFIG_SYS_LONGHELP
271 #define CONFIG_CMDLINE_EDITING 1
272 #define CONFIG_AUTO_COMPLETE
273 #define CONFIG_SYS_MAXARGS 64 /* max command args */
276 unsigned long get_dram_size_to_hide(void);
279 #define CONFIG_PANIC_HANG /* do not reset board on panic */
281 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
282 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
283 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
284 #define CONFIG_SPL_ENV_SUPPORT
285 #define CONFIG_SPL_FRAMEWORK
286 #define CONFIG_SPL_I2C_SUPPORT
287 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
288 #define CONFIG_SPL_LIBCOMMON_SUPPORT
289 #define CONFIG_SPL_LIBGENERIC_SUPPORT
290 #define CONFIG_SPL_MAX_SIZE 0x16000
291 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
292 #define CONFIG_SPL_NAND_SUPPORT
293 #define CONFIG_SPL_SERIAL_SUPPORT
294 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
295 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
296 #define CONFIG_SPL_TEXT_BASE 0x1800a000
298 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
299 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
300 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
301 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
302 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
304 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
307 #endif /* __LS2_COMMON_H */