2 * Copyright (C) 2014 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_SYS_GENERIC_BOARD
12 #define CONFIG_REMAKE_ELF
13 #define CONFIG_FSL_LSCH3
14 #define CONFIG_LS2085A
16 #define CONFIG_FSL_TZPC_BP147
19 #define CONFIG_ARM_ERRATA_828024
20 #define CONFIG_ARM_ERRATA_826974
22 #include <asm/arch-fsl-lsch3/config.h>
23 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
24 #define CONFIG_SYS_HAS_SERDES
27 /* We need architecture specific misc initializations */
28 #define CONFIG_ARCH_MISC_INIT
30 /* Link Definitions */
31 #define CONFIG_SYS_TEXT_BASE 0x30100000
34 #define CONFIG_SYS_NO_FLASH
37 #define CONFIG_SUPPORT_RAW_INITRD
39 #define CONFIG_SKIP_LOWLEVEL_INIT
40 #define CONFIG_BOARD_EARLY_INIT_F 1
42 /* Flat Device Tree Definitions */
43 #define CONFIG_OF_LIBFDT
44 #define CONFIG_OF_BOARD_SETUP
46 /* new uImage format support */
48 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
50 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
51 #ifndef CONFIG_SYS_FSL_DDR4
52 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
53 #define CONFIG_SYS_DDR_RAW_TIMING
56 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
58 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
59 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
60 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
61 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
62 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
67 #define CPU_RELEASE_ADDR secondary_boot_func
69 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
70 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
72 * DDR controller use 0 as the base address for binding.
73 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
75 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
76 #define CONFIG_DP_DDR_CTRL 2
77 #define CONFIG_DP_DDR_NUM_CTRLS 1
79 /* Generic Timer Definitions */
81 * This is not an accurate number. It is used in start.S. The frequency
82 * will be udpated later when get_bus_freq(0) is available.
84 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
86 /* Size of malloc() pool */
87 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
90 #define CONFIG_CMD_I2C
91 #define CONFIG_SYS_I2C
92 #define CONFIG_SYS_I2C_MXC
93 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
94 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
97 #define CONFIG_CONS_INDEX 2
98 #define CONFIG_SYS_NS16550
99 #define CONFIG_SYS_NS16550_SERIAL
100 #define CONFIG_SYS_NS16550_REG_SIZE 1
101 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
103 #define CONFIG_BAUDRATE 115200
104 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
107 #define CONFIG_FSL_IFC
110 * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
111 * address 0. But this region is limited to 256MB. To accommodate bigger NOR
112 * flash and other devices, we will map CS0 to 0x580000000 after relocation.
113 * CONFIG_SYS_FLASH_BASE has the final address (core view)
114 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
115 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
116 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
118 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
119 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
120 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
122 #ifndef CONFIG_SYS_NO_FLASH
123 #define CONFIG_FLASH_CFI_DRIVER
124 #define CONFIG_SYS_FLASH_CFI
125 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
126 #define CONFIG_SYS_FLASH_QUIET_TEST
129 #define CONFIG_SYS_NAND_BASE 0x520000000
130 #define CONFIG_SYS_NAND_BASE_PHYS 0x20000000
132 /* Debug Server firmware */
133 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
135 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
138 #define CONFIG_FSL_MC_ENET
139 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
140 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
141 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
142 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
143 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
144 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
146 /* Carve out a DDR region which will not be used by u-boot/Linux */
147 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
148 #define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide()
152 #define CONFIG_PCIE1 /* PCIE controler 1 */
153 #define CONFIG_PCIE2 /* PCIE controler 2 */
154 #define CONFIG_PCIE3 /* PCIE controler 3 */
155 #define CONFIG_PCIE4 /* PCIE controler 4 */
156 #define FSL_PCIE_COMPAT "fsl,20851a-pcie"
158 #define CONFIG_SYS_PCI_64BIT
160 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
161 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
162 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
163 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
165 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
166 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
167 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
169 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
170 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
171 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
173 /* Command line configuration */
174 #define CONFIG_CMD_CACHE
175 #define CONFIG_CMD_BDI
176 #define CONFIG_CMD_DHCP
177 #define CONFIG_CMD_ENV
178 #define CONFIG_CMD_FLASH
179 #define CONFIG_CMD_IMI
180 #define CONFIG_CMD_LOADB
181 #define CONFIG_CMD_MEMORY
182 #define CONFIG_CMD_MII
183 #define CONFIG_CMD_NET
184 #define CONFIG_CMD_PING
185 #define CONFIG_CMD_SAVEENV
186 #define CONFIG_CMD_RUN
187 #define CONFIG_CMD_BOOTD
188 #define CONFIG_CMD_ECHO
189 #define CONFIG_CMD_SOURCE
190 #define CONFIG_CMD_FAT
191 #define CONFIG_DOS_PARTITION
193 /* Miscellaneous configurable options */
194 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
195 #define CONFIG_ARCH_EARLY_INIT_R
197 /* Physical Memory Map */
198 /* fixme: these need to be checked against the board */
199 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
201 #define CONFIG_NR_DRAM_BANKS 3
203 #define CONFIG_HWCONFIG
204 #define HWCONFIG_BUFFER_SIZE 128
206 #define CONFIG_DISPLAY_CPUINFO
208 /* Initial environment variables */
209 #define CONFIG_EXTRA_ENV_SETTINGS \
210 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
211 "loadaddr=0x80100000\0" \
212 "kernel_addr=0x100000\0" \
213 "ramdisk_addr=0x800000\0" \
214 "ramdisk_size=0x2000000\0" \
215 "fdt_high=0xa0000000\0" \
216 "initrd_high=0xffffffffffffffff\0" \
217 "kernel_start=0x581200000\0" \
218 "kernel_load=0xa0000000\0" \
219 "kernel_size=0x1000000\0" \
220 "console=ttyAMA0,38400n8\0"
222 #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
223 "earlycon=uart8250,mmio,0x21c0600,115200 " \
224 "default_hugepagesz=2m hugepagesz=2m " \
226 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
227 "$kernel_size && bootm $kernel_load"
228 #define CONFIG_BOOTDELAY 1
230 /* Monitor Command Prompt */
231 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
232 #define CONFIG_SYS_PROMPT "=> "
233 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
234 sizeof(CONFIG_SYS_PROMPT) + 16)
235 #define CONFIG_SYS_HUSH_PARSER
236 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
237 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
238 #define CONFIG_SYS_LONGHELP
239 #define CONFIG_CMDLINE_EDITING 1
240 #define CONFIG_AUTO_COMPLETE
241 #define CONFIG_SYS_MAXARGS 64 /* max command args */
244 unsigned long get_dram_size_to_hide(void);
247 #define CONFIG_PANIC_HANG /* do not reset board on panic */
249 #endif /* __LS2_COMMON_H */