ARM: configs: Add da850evm_nand to boot from NAND
[oweals/u-boot.git] / include / configs / ls2080a_emu.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor
4  */
5
6 #ifndef __LS2_EMU_H
7 #define __LS2_EMU_H
8
9 #include "ls2080a_common.h"
10
11 #define CONFIG_SYS_CLK_FREQ     100000000
12 #define CONFIG_DDR_CLK_FREQ     133333333
13
14 #define CONFIG_DDR_SPD
15 #define CONFIG_SYS_FSL_DDR_EMU          /* Support emulator */
16 #define SPD_EEPROM_ADDRESS1     0x51
17 #define SPD_EEPROM_ADDRESS2     0x52
18 #define SPD_EEPROM_ADDRESS3     0x53
19 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
20 #define CONFIG_SYS_SPD_BUS_NUM  1       /* SPD on I2C bus 1 */
21 #define CONFIG_DIMM_SLOTS_PER_CTLR              1
22 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
23 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
24 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
25 #endif
26
27 #define CONFIG_FSL_DDR_SYNC_REFRESH
28
29 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
30 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
31 /*
32  * NOR Flash Timing Params
33  */
34 #define CONFIG_SYS_NOR0_CSPR                                    \
35         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
36         CSPR_PORT_SIZE_16                                       | \
37         CSPR_MSEL_NOR                                           | \
38         CSPR_V)
39 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
40         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
41         CSPR_PORT_SIZE_16                                       | \
42         CSPR_MSEL_NOR                                           | \
43         CSPR_V)
44 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
45 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
46                                 FTIM0_NOR_TEADC(0x1) | \
47                                 FTIM0_NOR_TEAHC(0x1))
48 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
49                                 FTIM1_NOR_TRAD_NOR(0x1))
50 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
51                                 FTIM2_NOR_TCH(0x0) | \
52                                 FTIM2_NOR_TWP(0x1))
53 #define CONFIG_SYS_NOR_FTIM3    0x04000000
54 #define CONFIG_SYS_IFC_CCR      0x01000000
55
56 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
57 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
58 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
59 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
60 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
61 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
62 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
63 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
64 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
65
66 /* Debug Server firmware */
67 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
68 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
69
70 /*
71  * This trick allows users to load MC images into DDR directly without
72  * copying from NOR flash. It dramatically improves speed.
73  */
74 #define CONFIG_SYS_LS_MC_FW_IN_DDR
75 #define CONFIG_SYS_LS_MC_DPL_IN_DDR
76 #define CONFIG_SYS_LS_MC_DPC_IN_DDR
77
78 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
79
80 /* Store environment at top of flash */
81 #define CONFIG_ENV_SIZE                 0x1000
82
83 #endif /* __LS2_EMU_H */