1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright (C) 2014 Freescale Semiconductor
10 #define CONFIG_REMAKE_ELF
13 #include <asm/arch/stream_id_lsch3.h>
14 #include <asm/arch/config.h>
16 /* Link Definitions */
18 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
23 /* We need architecture specific misc initializations */
25 /* Link Definitions */
26 #ifndef CONFIG_TFABOOT
27 #ifndef CONFIG_QSPI_BOOT
29 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
30 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
31 #define CONFIG_ENV_SECT_SIZE 0x40000
35 #define CONFIG_SKIP_LOWLEVEL_INIT
38 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
40 #ifndef CONFIG_SYS_FSL_DDR4
41 #define CONFIG_SYS_DDR_RAW_TIMING
44 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
46 #define CONFIG_VERY_BIG_RAM
47 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
48 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
50 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
51 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
56 #define CPU_RELEASE_ADDR secondary_boot_func
58 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
59 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
60 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
62 * DDR controller use 0 as the base address for binding.
63 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
65 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
66 #define CONFIG_DP_DDR_CTRL 2
67 #define CONFIG_DP_DDR_NUM_CTRLS 1
70 /* Generic Timer Definitions */
72 * This is not an accurate number. It is used in start.S. The frequency
73 * will be udpated later when get_bus_freq(0) is available.
75 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
77 /* Size of malloc() pool */
78 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
81 #define CONFIG_SYS_I2C
84 #define CONFIG_SYS_NS16550_SERIAL
85 #define CONFIG_SYS_NS16550_REG_SIZE 1
86 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
88 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
91 #define CONFIG_FSL_IFC
94 * During booting, IFC is mapped at the region of 0x30000000.
95 * But this region is limited to 256MB. To accommodate NOR, promjet
96 * and FPGA. This region is divided as below:
97 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
98 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
99 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
101 * To accommodate bigger NOR flash and other devices, we will map IFC
102 * chip selects to as below:
103 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
104 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
105 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
106 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
107 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
109 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
110 * CONFIG_SYS_FLASH_BASE has the final address (core view)
111 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
112 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
113 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
116 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
117 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
118 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
120 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
121 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
124 unsigned long long get_qixis_addr(void);
126 #define QIXIS_BASE get_qixis_addr()
127 #define QIXIS_BASE_PHYS 0x20000000
128 #define QIXIS_BASE_PHYS_EARLY 0xC000000
129 #define QIXIS_STAT_PRES1 0xb
130 #define QIXIS_SDID_MASK 0x07
131 #define QIXIS_ESDHC_NO_ADAPTER 0x7
133 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
134 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
137 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
138 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
139 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
140 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
141 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
143 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
144 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
146 /* Define phy_reset function to boot the MC based on mcinitcmd.
147 * This happens late enough to properly fixup u-boot env MAC addresses.
149 #define CONFIG_RESET_PHY_R
152 * Carve out a DDR region which will not be used by u-boot/Linux
154 * It will be used by MC and Debug Server. The MC region must be
155 * 512MB aligned, so the min size to hide is 512MB.
157 #ifdef CONFIG_FSL_MC_ENET
158 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
161 /* Command line configuration */
163 /* Miscellaneous configurable options */
164 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
166 /* Physical Memory Map */
167 /* fixme: these need to be checked against the board */
168 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
170 #define CONFIG_HWCONFIG
171 #define HWCONFIG_BUFFER_SIZE 128
173 /* Allow to overwrite serial and ethaddr */
174 #define CONFIG_ENV_OVERWRITE
176 /* Initial environment variables */
177 #define CONFIG_EXTRA_ENV_SETTINGS \
178 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
179 "loadaddr=0x80100000\0" \
180 "kernel_addr=0x100000\0" \
181 "ramdisk_addr=0x800000\0" \
182 "ramdisk_size=0x2000000\0" \
183 "fdt_high=0xa0000000\0" \
184 "initrd_high=0xffffffffffffffff\0" \
185 "kernel_start=0x581000000\0" \
186 "kernel_load=0xa0000000\0" \
187 "kernel_size=0x2800000\0" \
188 "console=ttyAMA0,38400n8\0" \
189 "mcinitcmd=fsl_mc start mc 0x580a00000" \
192 #ifndef CONFIG_TFABOOT
193 #ifdef CONFIG_SD_BOOT
194 #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\
195 " fsl_mc apply dpl 0x80200000 &&" \
196 " mmc read $kernel_load $kernel_start" \
197 " $kernel_size && bootm $kernel_load"
199 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
200 " cp.b $kernel_start $kernel_load" \
201 " $kernel_size && bootm $kernel_load"
205 /* Monitor Command Prompt */
206 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
207 #define CONFIG_SYS_MAXARGS 64 /* max command args */
209 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
210 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
211 #define CONFIG_SPL_MAX_SIZE 0x16000
212 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
213 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
214 #define CONFIG_SPL_TEXT_BASE 0x1800a000
216 #ifdef CONFIG_NAND_BOOT
217 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
218 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
220 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
221 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
222 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
224 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
226 #include <asm/arch/soc.h>
228 #endif /* __LS2_COMMON_H */