2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1043AQDS_H__
8 #define __LS1043AQDS_H__
10 #include "ls1043a_common.h"
12 #define CONFIG_DISPLAY_CPUINFO
13 #define CONFIG_DISPLAY_BOARDINFO
15 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
16 #define CONFIG_SYS_TEXT_BASE 0x82000000
17 #elif defined(CONFIG_QSPI_BOOT)
18 #define CONFIG_SYS_TEXT_BASE 0x40010000
20 #define CONFIG_SYS_TEXT_BASE 0x60100000
24 unsigned long get_board_sys_clk(void);
25 unsigned long get_board_ddr_clk(void);
28 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
29 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
31 #define CONFIG_SKIP_LOWLEVEL_INIT
33 #define CONFIG_LAYERSCAPE_NS_ACCESS
35 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
36 /* Physical Memory Map */
37 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
38 #define CONFIG_NR_DRAM_BANKS 2
40 #define CONFIG_DDR_SPD
41 #define SPD_EEPROM_ADDRESS 0x51
42 #define CONFIG_SYS_SPD_BUS_NUM 0
44 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
46 #define CONFIG_DDR_ECC
48 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
49 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
52 #ifdef CONFIG_SYS_DPAA_FMAN
53 #define CONFIG_FMAN_ENET
55 #define CONFIG_PHY_VITESSE
56 #define CONFIG_PHY_REALTEK
57 #define CONFIG_PHYLIB_10G
58 #define RGMII_PHY1_ADDR 0x1
59 #define RGMII_PHY2_ADDR 0x2
60 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
61 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
62 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
63 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
64 /* PHY address on QSGMII riser card on slot 1 */
65 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
66 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
67 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
68 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
69 /* PHY address on QSGMII riser card on slot 2 */
70 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
71 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
72 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
73 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
76 #ifdef CONFIG_RAMBOOT_PBL
77 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
80 #ifdef CONFIG_NAND_BOOT
81 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
85 #ifdef CONFIG_SD_BOOT_QSPI
86 #define CONFIG_SYS_FSL_PBL_RCW \
87 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
89 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
95 #define CONFIG_LPUART_32B_REG
100 #define CONFIG_SCSI_AHCI
101 #define CONFIG_SCSI_AHCI_PLAT
103 #define CONFIG_DOS_PARTITION
104 #define CONFIG_BOARD_LATE_INIT
107 #define CONFIG_ID_EEPROM
108 #define CONFIG_SYS_I2C_EEPROM_NXID
109 #define CONFIG_SYS_EEPROM_BUS_NUM 0
110 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
111 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
112 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
113 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
115 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
117 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
118 #define CONFIG_SYS_SCSI_MAX_LUN 1
119 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
120 CONFIG_SYS_SCSI_MAX_LUN)
125 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
126 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
127 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
128 CSPR_PORT_SIZE_16 | \
131 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
132 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
134 CSPR_PORT_SIZE_16 | \
137 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
139 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
141 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
142 FTIM0_NOR_TEADC(0x5) | \
143 FTIM0_NOR_TEAHC(0x5))
144 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
145 FTIM1_NOR_TRAD_NOR(0x1a) | \
146 FTIM1_NOR_TSEQRAD_NOR(0x13))
147 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
148 FTIM2_NOR_TCH(0x4) | \
149 FTIM2_NOR_TWPH(0xe) | \
151 #define CONFIG_SYS_NOR_FTIM3 0
153 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
154 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
155 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
156 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
158 #define CONFIG_SYS_FLASH_EMPTY_INFO
159 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
160 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
162 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
163 #define CONFIG_SYS_WRITE_SWAPPED_DATA
166 * NAND Flash Definitions
168 #define CONFIG_NAND_FSL_IFC
170 #define CONFIG_SYS_NAND_BASE 0x7e800000
171 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
173 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
175 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
179 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
180 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
181 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
182 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
183 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
184 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
185 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
186 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
188 #define CONFIG_SYS_NAND_ONFI_DETECTION
190 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
191 FTIM0_NAND_TWP(0x18) | \
192 FTIM0_NAND_TWCHT(0x7) | \
194 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
195 FTIM1_NAND_TWBE(0x39) | \
196 FTIM1_NAND_TRR(0xe) | \
197 FTIM1_NAND_TRP(0x18))
198 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
199 FTIM2_NAND_TREH(0xa) | \
200 FTIM2_NAND_TWHRE(0x1e))
201 #define CONFIG_SYS_NAND_FTIM3 0x0
203 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
204 #define CONFIG_SYS_MAX_NAND_DEVICE 1
205 #define CONFIG_MTD_NAND_VERIFY_WRITE
206 #define CONFIG_CMD_NAND
208 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
211 #ifdef CONFIG_NAND_BOOT
212 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
213 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
214 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
217 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
218 #define CONFIG_QIXIS_I2C_ACCESS
219 #define CONFIG_SYS_I2C_EARLY_INIT
220 #define CONFIG_SYS_NO_FLASH
226 #define CONFIG_FSL_QIXIS
228 #ifdef CONFIG_FSL_QIXIS
229 #define QIXIS_BASE 0x7fb00000
230 #define QIXIS_BASE_PHYS QIXIS_BASE
231 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
232 #define QIXIS_LBMAP_SWITCH 6
233 #define QIXIS_LBMAP_MASK 0x0f
234 #define QIXIS_LBMAP_SHIFT 0
235 #define QIXIS_LBMAP_DFLTBANK 0x00
236 #define QIXIS_LBMAP_ALTBANK 0x04
237 #define QIXIS_LBMAP_NAND 0x09
238 #define QIXIS_LBMAP_SD 0x00
239 #define QIXIS_LBMAP_SD_QSPI 0xff
240 #define QIXIS_LBMAP_QSPI 0xff
241 #define QIXIS_RCW_SRC_NAND 0x106
242 #define QIXIS_RCW_SRC_SD 0x040
243 #define QIXIS_RCW_SRC_QSPI 0x045
244 #define QIXIS_RST_CTL_RESET 0x41
245 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
246 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
247 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
249 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
250 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
254 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
255 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
256 CSOR_NOR_NOR_MODE_AVD_NOR | \
260 * QIXIS Timing parameters for IFC GPCM
262 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
263 FTIM0_GPCM_TEADC(0x20) | \
264 FTIM0_GPCM_TEAHC(0x10))
265 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
266 FTIM1_GPCM_TRAD(0x1f))
267 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
268 FTIM2_GPCM_TCH(0x8) | \
269 FTIM2_GPCM_TWP(0xf0))
270 #define CONFIG_SYS_FPGA_FTIM3 0x0
273 #ifdef CONFIG_NAND_BOOT
274 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
275 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
276 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
277 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
278 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
279 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
280 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
281 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
282 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
283 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
284 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
285 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
286 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
287 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
288 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
289 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
290 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
291 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
292 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
293 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
294 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
295 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
296 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
297 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
298 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
299 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
300 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
301 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
302 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
303 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
304 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
305 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
307 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
308 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
309 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
310 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
311 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
312 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
313 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
314 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
315 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
316 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
317 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
318 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
319 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
320 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
321 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
322 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
323 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
324 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
325 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
326 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
327 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
328 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
329 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
330 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
331 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
332 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
333 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
334 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
335 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
336 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
337 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
338 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
342 * I2C bus multiplexer
344 #define I2C_MUX_PCA_ADDR_PRI 0x77
345 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
346 #define I2C_RETIMER_ADDR 0x18
347 #define I2C_MUX_CH_DEFAULT 0x8
348 #define I2C_MUX_CH_CH7301 0xC
349 #define I2C_MUX_CH5 0xD
350 #define I2C_MUX_CH7 0xF
352 #define I2C_MUX_CH_VOL_MONITOR 0xa
354 /* Voltage monitor on channel 2*/
355 #define I2C_VOL_MONITOR_ADDR 0x40
356 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
357 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
358 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
360 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
361 #ifndef CONFIG_SPL_BUILD
364 #define CONFIG_VOL_MONITOR_IR36021_SET
365 #define CONFIG_VOL_MONITOR_INA220
366 /* The lowest and highest voltage allowed for LS1043AQDS */
367 #define VDD_MV_MIN 819
368 #define VDD_MV_MAX 1212
371 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
372 #define CONFIG_FSL_QSPI
373 #ifdef CONFIG_FSL_QSPI
374 #define CONFIG_SPI_FLASH_SPANSION
375 #define FSL_QSPI_FLASH_SIZE (1 << 24)
376 #define FSL_QSPI_FLASH_NUM 2
381 #define CONFIG_HAS_FSL_XHCI_USB
382 #ifdef CONFIG_HAS_FSL_XHCI_USB
383 #define CONFIG_USB_XHCI_FSL
384 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
385 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
389 * Miscellaneous configurable options
391 #define CONFIG_MISC_INIT_R
392 #define CONFIG_SYS_LONGHELP /* undef to save memory */
393 #define CONFIG_AUTO_COMPLETE
394 #define CONFIG_SYS_PBSIZE \
395 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
396 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
398 #define CONFIG_SYS_MEMTEST_START 0x80000000
399 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
401 #define CONFIG_SYS_HZ 1000
405 * The stack sizes are set up in start.S using the settings below
407 #define CONFIG_STACKSIZE (30 * 1024)
409 #define CONFIG_SYS_INIT_SP_OFFSET \
410 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
412 #ifdef CONFIG_SPL_BUILD
413 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
415 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
421 #define CONFIG_ENV_OVERWRITE
423 #ifdef CONFIG_NAND_BOOT
424 #define CONFIG_ENV_IS_IN_NAND
425 #define CONFIG_ENV_SIZE 0x2000
426 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
427 #elif defined(CONFIG_SD_BOOT)
428 #define CONFIG_ENV_OFFSET (1024 * 1024)
429 #define CONFIG_ENV_IS_IN_MMC
430 #define CONFIG_SYS_MMC_ENV_DEV 0
431 #define CONFIG_ENV_SIZE 0x2000
432 #elif defined(CONFIG_QSPI_BOOT)
433 #define CONFIG_ENV_IS_IN_SPI_FLASH
434 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
435 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
436 #define CONFIG_ENV_SECT_SIZE 0x10000
438 #define CONFIG_ENV_IS_IN_FLASH
439 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
440 #define CONFIG_ENV_SECT_SIZE 0x20000
441 #define CONFIG_ENV_SIZE 0x20000
444 #define CONFIG_CMDLINE_TAG
446 #include <asm/fsl_secure_boot.h>
448 #endif /* __LS1043AQDS_H__ */