include/configs/ls1043aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1043AQDS_H__
   7 #define __LS1043AQDS_H__
   8
   9 #include "ls1043a_common.h"
  10
  11 #ifndef __ASSEMBLY__
  12 unsigned long get_board_sys_clk(void);
  13 unsigned long get_board_ddr_clk(void);
  14 #endif
  15
  16 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  17 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20
  21 #define CONFIG_LAYERSCAPE_NS_ACCESS
  22
  23 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  24 /* Physical Memory Map */
  25 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  26
  27 #define CONFIG_DDR_SPD
  28 #define SPD_EEPROM_ADDRESS              0x51
  29 #define CONFIG_SYS_SPD_BUS_NUM          0
  30
  31 #ifndef CONFIG_SPL
  32 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  33 #endif
  34
  35 #define CONFIG_DDR_ECC
  36 #ifdef CONFIG_DDR_ECC
  37 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  38 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  39 #endif
  40
  41 #ifdef CONFIG_SYS_DPAA_FMAN
  42 #define CONFIG_FMAN_ENET
  43 #define CONFIG_PHY_VITESSE
  44 #define CONFIG_PHY_REALTEK
  45 #define CONFIG_PHYLIB_10G
  46 #define RGMII_PHY1_ADDR         0x1
  47 #define RGMII_PHY2_ADDR         0x2
  48 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  49 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  50 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  51 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  52 /* PHY address on QSGMII riser card on slot 1 */
  53 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
  54 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
  55 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
  56 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
  57 /* PHY address on QSGMII riser card on slot 2 */
  58 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  59 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  60 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  61 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  62 #endif
  63
  64 #ifdef CONFIG_RAMBOOT_PBL
  65 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
  66 #endif
  67
  68 #ifdef CONFIG_NAND_BOOT
  69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
  70 #endif
  71
  72 #ifdef CONFIG_SD_BOOT
  73 #ifdef CONFIG_SD_BOOT_QSPI
  74 #define CONFIG_SYS_FSL_PBL_RCW \
  75         board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
  76 #else
  77 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
  78 #endif
  79 #endif
  80
  81 /* LPUART */
  82 #ifdef CONFIG_LPUART
  83 #define CONFIG_LPUART_32B_REG
  84 #endif
  85
  86 /* SATA */
  87 #define CONFIG_SCSI_AHCI_PLAT
  88
  89 /* EEPROM */
  90 #define CONFIG_ID_EEPROM
  91 #define CONFIG_SYS_I2C_EEPROM_NXID
  92 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  93 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
  94 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
  95 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
  96 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
  97
  98 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
  99
 100 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
 101 #define CONFIG_SYS_SCSI_MAX_LUN                 1
 102 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 103                                                 CONFIG_SYS_SCSI_MAX_LUN)
 104
 105 /*
 106  * IFC Definitions
 107  */
 108 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 109 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 110 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 111                                 CSPR_PORT_SIZE_16 | \
 112                                 CSPR_MSEL_NOR | \
 113                                 CSPR_V)
 114 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 115 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 116                                 + 0x8000000) | \
 117                                 CSPR_PORT_SIZE_16 | \
 118                                 CSPR_MSEL_NOR | \
 119                                 CSPR_V)
 120 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 121
 122 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 123                                         CSOR_NOR_TRHZ_80)
 124 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 125                                         FTIM0_NOR_TEADC(0x5) | \
 126                                         FTIM0_NOR_TEAHC(0x5))
 127 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 128                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 129                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 130 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 131                                         FTIM2_NOR_TCH(0x4) | \
 132                                         FTIM2_NOR_TWPH(0xe) | \
 133                                         FTIM2_NOR_TWP(0x1c))
 134 #define CONFIG_SYS_NOR_FTIM3            0
 135
 136 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 137 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 138 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 139 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 140
 141 #define CONFIG_SYS_FLASH_EMPTY_INFO
 142 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 143                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 144
 145 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 146 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 147
 148 /*
 149  * NAND Flash Definitions
 150  */
 151 #define CONFIG_NAND_FSL_IFC
 152
 153 #define CONFIG_SYS_NAND_BASE            0x7e800000
 154 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 155
 156 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 157
 158 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 159                                 | CSPR_PORT_SIZE_8      \
 160                                 | CSPR_MSEL_NAND        \
 161                                 | CSPR_V)
 162 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 163 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 164                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 165                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 166                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 167                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 168                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 169                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 170
 171 #define CONFIG_SYS_NAND_ONFI_DETECTION
 172
 173 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 174                                         FTIM0_NAND_TWP(0x18)   | \
 175                                         FTIM0_NAND_TWCHT(0x7) | \
 176                                         FTIM0_NAND_TWH(0xa))
 177 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 178                                         FTIM1_NAND_TWBE(0x39)  | \
 179                                         FTIM1_NAND_TRR(0xe)   | \
 180                                         FTIM1_NAND_TRP(0x18))
 181 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 182                                         FTIM2_NAND_TREH(0xa) | \
 183                                         FTIM2_NAND_TWHRE(0x1e))
 184 #define CONFIG_SYS_NAND_FTIM3           0x0
 185
 186 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 187 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 188 #define CONFIG_MTD_NAND_VERIFY_WRITE
 189
 190 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 191 #endif
 192
 193 #ifdef CONFIG_NAND_BOOT
 194 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 195 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 196 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 << 10)
 197 #endif
 198
 199 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 200 #define CONFIG_QIXIS_I2C_ACCESS
 201 #define CONFIG_SYS_I2C_EARLY_INIT
 202 #endif
 203
 204 /*
 205  * QIXIS Definitions
 206  */
 207 #define CONFIG_FSL_QIXIS
 208
 209 #ifdef CONFIG_FSL_QIXIS
 210 #define QIXIS_BASE                      0x7fb00000
 211 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 212 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 213 #define QIXIS_LBMAP_SWITCH              6
 214 #define QIXIS_LBMAP_MASK                0x0f
 215 #define QIXIS_LBMAP_SHIFT               0
 216 #define QIXIS_LBMAP_DFLTBANK            0x00
 217 #define QIXIS_LBMAP_ALTBANK             0x04
 218 #define QIXIS_LBMAP_NAND                0x09
 219 #define QIXIS_LBMAP_SD                  0x00
 220 #define QIXIS_LBMAP_SD_QSPI             0xff
 221 #define QIXIS_LBMAP_QSPI                0xff
 222 #define QIXIS_RCW_SRC_NAND              0x106
 223 #define QIXIS_RCW_SRC_SD                0x040
 224 #define QIXIS_RCW_SRC_QSPI              0x045
 225 #define QIXIS_RST_CTL_RESET             0x41
 226 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 227 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 228 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 229
 230 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 231 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 232                                         CSPR_PORT_SIZE_8 | \
 233                                         CSPR_MSEL_GPCM | \
 234                                         CSPR_V)
 235 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 236 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 237                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 238                                         CSOR_NOR_TRHZ_80)
 239
 240 /*
 241  * QIXIS Timing parameters for IFC GPCM
 242  */
 243 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 244                                         FTIM0_GPCM_TEADC(0x20) | \
 245                                         FTIM0_GPCM_TEAHC(0x10))
 246 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 247                                         FTIM1_GPCM_TRAD(0x1f))
 248 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 249                                         FTIM2_GPCM_TCH(0x8) | \
 250                                         FTIM2_GPCM_TWP(0xf0))
 251 #define CONFIG_SYS_FPGA_FTIM3           0x0
 252 #endif
 253
 254 #ifdef CONFIG_NAND_BOOT
 255 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 256 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 257 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 258 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 259 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 260 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 261 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 262 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 263 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 264 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 265 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 266 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 267 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 268 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 269 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 270 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 271 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 272 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 273 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 274 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 275 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 276 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 277 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 278 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 279 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 280 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 281 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 282 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 283 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 284 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 285 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 286 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 287 #else
 288 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 289 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 290 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 291 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 292 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 293 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 294 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 295 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 296 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 297 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 298 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 299 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 300 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 301 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 302 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 303 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 304 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 305 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 306 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 307 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 308 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 309 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 310 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 311 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 312 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 313 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 314 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 315 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 316 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 317 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 318 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 319 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 320 #endif
 321
 322 /*
 323  * I2C bus multiplexer
 324  */
 325 #define I2C_MUX_PCA_ADDR_PRI            0x77
 326 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 327 #define I2C_RETIMER_ADDR                0x18
 328 #define I2C_MUX_CH_DEFAULT              0x8
 329 #define I2C_MUX_CH_CH7301               0xC
 330 #define I2C_MUX_CH5                     0xD
 331 #define I2C_MUX_CH7                     0xF
 332
 333 #define I2C_MUX_CH_VOL_MONITOR 0xa
 334
 335 /* Voltage monitor on channel 2*/
 336 #define I2C_VOL_MONITOR_ADDR           0x40
 337 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 338 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 339 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 340
 341 #define CONFIG_VID_FLS_ENV              "ls1043aqds_vdd_mv"
 342 #ifndef CONFIG_SPL_BUILD
 343 #define CONFIG_VID
 344 #endif
 345 #define CONFIG_VOL_MONITOR_IR36021_SET
 346 #define CONFIG_VOL_MONITOR_INA220
 347 /* The lowest and highest voltage allowed for LS1043AQDS */
 348 #define VDD_MV_MIN                      819
 349 #define VDD_MV_MAX                      1212
 350
 351 /* QSPI device */
 352 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 353 #define CONFIG_FSL_QSPI
 354 #ifdef CONFIG_FSL_QSPI
 355 #define CONFIG_SPI_FLASH_SPANSION
 356 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 357 #define FSL_QSPI_FLASH_NUM              2
 358 #endif
 359 #endif
 360
 361 /*
 362  * Miscellaneous configurable options
 363  */
 364
 365 #define CONFIG_SYS_MEMTEST_START        0x80000000
 366 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 367
 368 #define CONFIG_SYS_HZ                   1000
 369
 370 #define CONFIG_SYS_INIT_SP_OFFSET \
 371         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 372
 373 #ifdef CONFIG_SPL_BUILD
 374 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 375 #else
 376 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 377 #endif
 378
 379 /*
 380  * Environment
 381  */
 382 #define CONFIG_ENV_OVERWRITE
 383
 384 #ifdef CONFIG_NAND_BOOT
 385 #define CONFIG_ENV_SIZE                 0x2000
 386 #define CONFIG_ENV_OFFSET               (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
 387 #elif defined(CONFIG_SD_BOOT)
 388 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
 389 #define CONFIG_SYS_MMC_ENV_DEV          0
 390 #define CONFIG_ENV_SIZE                 0x2000
 391 #elif defined(CONFIG_QSPI_BOOT)
 392 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 393 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
 394 #define CONFIG_ENV_SECT_SIZE            0x10000
 395 #else
 396 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 397 #define CONFIG_ENV_SECT_SIZE            0x20000
 398 #define CONFIG_ENV_SIZE                 0x20000
 399 #endif
 400
 401 #define CONFIG_CMDLINE_TAG
 402
 403 #include <asm/fsl_secure_boot.h>
 404
 405 #endif /* __LS1043AQDS_H__ */